JPS5922278A - Writing method of memory - Google Patents

Abstract

PURPOSE:To shorten the transfer time of data to memory planes by adopting a read modify write mode for the writing of the memory plane and automatically switching memory plate selection at the end of a read period in the read and write periods. CONSTITUTION:The writing of the memory planes 7-10 is set up so as to be executed at the read modify write mode. During the read period, reading data 32-35 are read out in accordance with an address 15 and a chip selector 17 outputted from a display controlling circuit 1 and the reading data from one memory plane selected in accordance with reading plane selecting signals 18-21 are outputted by bus drivers 11-14 as the reading data 23 and supplied to the display controlling circuit 1. During the write period following the read period, write specifying signals 28-31 are outputted from a write specification controlling circuit 6 when a delay enabling signal 41 obtained by delaying a bus enabling signal 22 by a delay circuit 4 is supplied, so that writing to an single or plural memory planes specified by the write plane selecting circuit 5 is made available.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory writing system, and more particularly to a memory writing system that is composed of several planes and used for writing into an image memory of a color graphic CRT, for example.

Conventional memory writing methods have a memory plane select register that is set by the processor, and enable or disable reading and writing to a certain memory plane according to the contents set in this memory plane select register. .

Therefore, in such a conventional memory write method, when data is transferred from one memory plane to another, K first indicates which plane is to be read into the memory plane select register. Set the read plane select signal and transfer the data to the main memory 17. After the transfer is complete, set the write plane select signal that indicates the memory plane to be written to in the memory plane select register, and transfer the data from the main memory to the memory plane again. It took a lot of effort to do it twice.

Therefore, the conventional memory writing method has the disadvantage that it takes a long time to transfer data between memory planes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory write method that can reduce the time required to transfer data between memory planes.

That is, an object of the present invention is to adopt read-modify-write mode for reading and writing screen memory, and when reading, read from a single plane, and when writing, write to a single plane or multiple planes simultaneously according to the contents of the set register. By doing this, when transferring data from one memory plane to another memory plane, it is not necessary to first transfer the data to main memory and then transfer the transferred data to another plane. Without,
To provide a memory write method that can shorten data transfer time by transferring data to a main memory and simultaneously transferring it to another plane, or by simultaneously transferring data to another plane such as pseudo writing that does not change the contents. There is a particular thing.

The memory write method of the present invention has a plurality of memory planes in which data is read and written according to addresses, and when a first bus enable signal generated in response to a read period in read-modify-write mode is supplied. a second memory plane that specifies a memory plane that supplies read data among the memory planes in response to a read plane select signal;
a bus enable circuit that outputs a bus enable signal; a delay circuit that outputs a generated delay enable signal;
a write plane select circuit that outputs a write plane select signal; and a write plane select circuit that outputs a write plane select signal, and a write plane that indicates a memory plane to which write data is written among the planes in response to the write plane select signal when the delay enable signal is supplied. and a write instruction control circuit that outputs a write instruction signal.

In the control circuit for writing data, a first means for delaying an enable signal for loading read data read in the first read period onto a read data bus, and a select signal for selecting a memory plane for writing data are output. The device includes a second means, and a third means for generating a write instruction signal to the memory plane based on the signals output from the first means and the second means.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. 1 shows an example in which the rope ribbed consists of four planes.

The memory writing method shown in Figure 1 is the bus interface 2.
display control circuit 1 connected to the processor via the display control circuit 1, and memory planes 7.8, 9.1 to which addresses 15 and write data 16 output from the display control circuit 1 are supplied.
0, bus drivers 1, 1, 12, 13, 14 to which read data 32, 33, 34, 35 output from memory planes 7 to 10 are respectively supplied, and a read plane output from display control circuit 1. Selec) Shin 18, 19
, 20° 21 and a bus enable signal 22 and outputs bus enable signals 24 to 27; a delay circuit 4 that delays the bus enable signal 22 and outputs a delayed enable signal 41; A write plane select circuit 5 outputs write plane select signals 37 to 40 set via an interface 36, and when a delay enable signal 41 is supplied, write plane select signals 37 to 40 are output.
The write instruction control circuit 6 generates write instruction signals 28 to 31 according to the write instruction signals 28 to 31.

During the interval, read data 32 to 35 are read from each memory plane 7 to 10 according to the address 15 and chip select 17 output from the display control circuit 1, and a certain one selected according to the read plane select signals 18, 19, 20, 21 is read. The read data from the memory plane (for example, memory plane 7) is transferred to the bus drivers 11, 12.1.
3.14) is output as read data 23 and supplied to the display control circuit 1.

During the write period following the read in the read-modify-write mode, the bus enable signal 22 is output to the delay circuit 4.
When the delayed enable signal 4J obtained by delaying is supplied, the write instruction control circuit 6 outputs the write instruction signal 28.2.
9.30.31 is output, and writing to the single or multiple memory planes instructed by the write plane select circuit 5 becomes valid.

When transferring data from one memory plane to another, for example, memory plane 8°9.10 3
The plane is used for screen display, and the other memory plane 7 is used as a work plane and transferred to the used plane. Therefore, in the lead period, −,.

Only the memory plane select signal 18 is set from the display control circuit 1 to specify the memory plane 7 as the work plane, and the memory planes 8 to 10 are set as the memory planes to which data is to be transferred to the write plane select circuit 5.
If the write plane select signals 38 to 40 indicating the above are set, data transfer is completed by reading the read data 32 from the memory plane 7 or by performing a pseudo write that does not change the contents of the memory plane 7.

Therefore, it is possible to omit the need to temporarily transfer the contents of the work plane to the main memory and then transfer the data to the memory plane to which data is to be written.

By adding a write plane select circuit, the memory write method of the present invention allows the memory plane that supplies read data and the memory plane to which write data is written to be specified simultaneously instead of sequentially. Therefore, instead of storing successive data in the -H main memory and then writing it to another memory plane, read data can be immediately written to another memory plane, reducing data transfer time between memory planes. There is an effect that it can be done.

That is, the memory write method of the present invention employs a read-modify-write mode for memory plane writing, and is configured to automatically switch the memory plane select between the read period and the write period after the read period ends. This has the effect of shortening the data transfer time from the memory plane to the memory plane and the processor processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Display control circuit, 2.36...Bus interface, 3...Bus enable circuit, 4...Delay circuit, 5...・Write plane select circuit, 6...Write instruction control circuit,
7.8,9.10...Memory plane, 11,
12,13.14...ノ(sdriver, 15.
...Address, 16...Write data, 1
7... Chip select, 18, 19.20゜2
1,... Read plane select signal, 22...
...) Bus enable signal, 23... Read data, 24°25.26.27... Bus enable signal, 28°29.30.31... Write instruction signal, 32, 33° 34, . 35...Read data, 37, 38, 39°40...Write plane select signal, 41...Delay enable signal.

Claims (1)

[Claims] A plurality of memory planes in which data is read and written according to the address, and a plurality of memory planes in which data is read and written according to the address, and the first bus enable signal generated corresponding to the read period in the read modify write mode are supplied, A delay circuit that outputs a delay enable signal generated in response to a pulse write period that outputs a second bus enable signal instructing a memory plane that supplies read data among the memory planes, and a bus enable signal that outputs a write plane select signal. a write plane select circuit, and a write instruction for outputting a write instruction signal indicative of a memory plane to which write data is to be written among the planes in response to the write plane select signal when the delay enable signal is supplied. A memory writing method characterized by comprising a control circuit.