JPS58189719A - Data transfer control system - Google Patents

Abstract

PURPOSE:To perform processing at a high speed, by providing plural data areas within a main storage device and performing a DMA transfer while switching the data areas during the transfer of the data. CONSTITUTION:This system includes a size register 1 which sets the size of the data area of a main storage device MM by the information given from a CPU via an input/output bus 6 and a bus interface 7, a buffer number register 2 which sets the number of data areas of the MM, and address registers 3-5 which set the start address of each data area of the MM. A multiplexer MPX8 selects the start addresses given from the registers 3-5 and then delivers them to the MM via an interface 9 and a DMA bus 10. The input data is stored to an internal memory of an FIFO circuit 13. When the use of the bus 10 is permitted, a data is delivered to the data area of the MM from an address selected by an MPX8. A counter 11 counts down to switch the data area every time when the data on only the size set to the register 1 is transferred.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer system in an electronic computer, and more particularly to an improvement in a direct memory access transfer system.

2. Description of the Related Art A direct memory access (hereinafter abbreviated as DMA) transfer method for directly transferring data to a main storage device is known as a data transfer method for conventional point-counter systems. By the way, in data transfer in a DMA type analog input device that performs such a transfer method, data corresponding to a specified number of points is transferred to a specified data area of the main storage device. After this transfer is completed, the data is used or copied to another input/output device. However, in such a system, when each point is repeatedly sampled and the data is read, the amount of data increases and the processing speed inevitably decreases.

The present invention has been made in view of the circumstances mentioned in section t.The present invention provides data transfer control that enables high-speed processing by providing a plurality of data areas in the main memory and performing a DMA transfer method while switching these data areas during data transfer. The purpose is to provide a method.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG. vI1. In the figure, 1 is a size register that stores the size of the data area in the main memory, 2 is a buffer number register that stores the number of data areas in the main memory, and 3.4.5 is the start of the data area in the main memory. These are first to third address registers that store addresses. Note that each of the above registers 1 to 5 is connected to an input/output bus 6 from a central processing unit (not shown) at the time of initial setting.
And desired data is set via the interface 7.

8 indicates each of the first to third address registers 3, 4 .
This multiplexer selects a start address from 5 and outputs it via the DMA bus interface 9 and DMk bus 10 to designate the start address in the main memory.

Further, numeral 11 is a counter that counts down each time a DMA transfer is performed to the main storage device, and provides this count value to the controller 12. Note that 13 is a predecessor circuit ()i'1 having an internal memory that temporarily stores digital data generated by λ/D conversion on an analog board, for example.
Fo).

With such a configuration, initial setting information is set in each register 1, 2, . . . 5 from a central processing unit (not shown) via an input/output bus 6 and an interface 7. Thereafter, in response to a start signal for DMA transfer from the central processing unit, a sampling start signal is given to the analog board, for example, to sample the analog signal, convert it to a digital signal, and output it. Also, the contents of the size register 1 are loaded into the counter 1, and a predetermined address is selected from the first to third address registers 3, 4.5 by the multiplexer 8 according to this value and the output of the buffer number register 2. . The digital data sent from the analog board F is stored in the internal memory of the first-in, first-out circuit 13, and when the DMA bus is enabled, the data is transferred from the address selected by the multiplexer 8 to, for example, the first data area of the main memory. Output. Each time the data transfer is completed by the size set in size register 1, the counter 1 is counted down, and when a borrow signal is output, the area of the main memory where the data is being transferred becomes full. judge it as something. Then, the next address register is selected by the multiplexer 8, and the next data is output to the second data area of the main memory and stored therein. At this time, the counter 11 loads the contents of the size register 1 again, and the central processing unit
\Set status data to notify that data has been switched and generate an interrupt. The input data is then transferred to the second data area of the main storage device by DMA transfer. Then, when the borrow signal is output again from the counter 1, the contents of the third address register 5 are selected by the multiplexer 8 and switched to the third data area of the main memory. Even if the third data area of the main memory is full, if further data is to be sent from the analog board, the contents of the first address register 3 are again selected by the multiplexer 8 and written to the main memory. The first data area/data area of is transferred.

That is, the stored data in the main memory is stored in the first . Second. third data area D,
, D2. D3 are sequentially distributed, and each leading address AIrA2+A3 is assigned to address registers 3, 4.5.
becomes the start address specified by . Note that the number of data areas is not limited to three areas, and it goes without saying that an appropriate number of areas can be set. It goes without saying that the arrangement, switching order, etc. can be set as appropriate.

When a DMA transfer is performed in this way, the central processing unit can know the selected data area by the interrupt signal and status data when the address registers 3, 4.5 are switched, and for example, when the data transfer is completed, Copy the data in the data area to another input/output device.

As described in detail below, in the present invention, a plurality of data areas are provided in the main memory, and the data areas are sequentially switched and used during DMA transfer. A large amount of data can be transferred at high speed, and processing speed can be increased. Furthermore, by performing DMA transfer, data in other data areas can be copied to input/output equipment etc. via the input/output path while transferring data using the DMA bus. Therefore, by using these data transfers in parallel, it is possible to provide a data transfer control system that considers whether a large amount of data can be transferred at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing a memory map of the L era embodiment. 1...Size register 2...Buffer number register 3.4.5...Address register 6...I/O bus 8...Multiplexer 10...DMA path 11 -Counter

Claims (1)

[Claims] When input data is transferred to multiple data areas in the main memory via a direct memory access path using the direct memory access transfer method, the size of the data area in the main memory is set based on information given from the central processing unit. A size register for setting the number of data areas provided in the main storage device based on information given from the central processing unit, and a buffer number register for setting the number of data areas provided in the main storage device, are provided corresponding to each data area of the fertilization storage device. An address register in which the start address of each data area of the main memory is set based on information provided by the device, a multiplexer that sequentially selects the start address set in each address register, and direct memory access provided by the central processing unit. A method in which the value of the size register is set in response to a command from the controller, and the multiplexer is controlled every time the set value matches the number of transferred data.