JP2531209B2 - Channel device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel device, and more particularly, to data transfer between a channel and a main storage device in units of a plurality of bytes, and between the channel and an input / output device. The present invention relates to a byte multiplexer channel device in which data transfer is performed byte by byte.

[Conventional technology]

Normally, when transferring data between a channel and an I / O device, first the I / O command from the CPU activates the channel and I / O device, and then the channel
It operates in parallel with the CPU to perform data transfer processing between the channel and the input / output device and the main storage device in a predetermined sequence. In the above-mentioned byte multiplexer channel device, the channel reads out a plurality of bytes of data from the main storage device, temporarily stores them, and transfers them to the input / output device for each 1-byte data. It is performed by executing a series of processing including a plurality of steps in a predetermined sequence. Therefore, in order to transfer all the data of multiple bytes once stored in the channel to the input / output device,
It is necessary to repeat the series of processes performed in the predetermined sequence described above. The conventional byte multiplexer channel device is configured to issue a memory fetch request for requesting data transmission to the main memory device for each series of processes.

[Problems to be solved by the invention]

The above-mentioned conventional byte multiplexer channel device issues a memory fetch request for requesting data transmission to the main memory device for each series of processing, so the number of accesses to the main memory device increases and Data transfer of the multiplexer channel cannot be performed at high speed,
Furthermore, there is a drawback that it interferes with the processing of other devices such as the block multiplexer channel and the CPU.

[Means for solving problems]

The channel device of the present invention should temporarily store a plurality of bytes of data read from the main storage device and send out each byte of data to the input / output device; and a data buffer to be transferred from the main storage device. Memory fetch request means for sending a memory fetch request for reading data and storing it in the data buffer to the main storage device, and detecting and detecting whether or not data exists in the data buffer. A data amount detecting means for sending a signal to the memory fetch requesting means, a byte multiplexer channel device and an input / output device are activated by an input / output instruction from the CPU, and then a predetermined sequence is performed from the input / output device to which data transfer is to be performed. When a request to perform processing is input to the byte multiplexer channel device, the request is sent. Take in the device address of the issued I / O device as the I / O address,
A first input / output address holding means for temporarily holding and an input / output address held in the first input / output address holding means while the data transfer processing is executed according to the predetermined sequence. , The second input / output address holding means for holding, and the byte multiplexer channel for requesting execution of processing in the predetermined sequence from the input / output device to which data transfer is to be performed after the predetermined sequence is completed. When input to the device, the input / output address fetched by the first input / output address holding means is compared with the input / output address held by the second input / output address holding means. Detect those matches / mismatches,
And an input / output address comparison means for sending a match detection signal when these matches are detected and a signal for forcing a memory fetch request to be sent to the memory fetch request means when a mismatch is detected. When the match detection signal from the input / output address comparison unit is input, and it is confirmed by the detection signal from the data amount detection unit that the data is held in the data buffer, Does not send a memory fetch request, but if there is no data in the data buffer even if a match detection signal is input from the input / output address comparison means, or a signal that forces a memory fetch request from the input / output address comparison circuit is input. Configured to send a memory fetch request to main memory when If no request is sent, the byte multiplexer channel device is configured to perform sequencing using the data held in the data buffer.

[Action]

When accessing multiple I / O devices,
The data to be transferred to each I / O device is stored in different areas in the main memory corresponding to those I / O devices, and the byte multiplexer channel device performs the write operation (data transfer to the I / O device). When writing and inputting various control signals to the input / output device), when the input / output device to be accessed is different (that is, when the input / output address (device number) is different), It is necessary to store the data corresponding to the I / O device that is going to transfer data by issuing a memory fetch request to the main memory device, but when accessing the same I / O device continuously. In many cases, the untransferred data held in the data buffer can be used. In this case, it is possible to send a memory fetch request. Not. With this in mind, the I / O address comparison means detects that the I / O device accessed in the previous sequence and the I / O device attempting to access in the current sequence are the same, and the data buffer previously stored If the fetched data remains during the sequence of, the number of memory accesses can be reduced by transferring the remaining data without sending a new memory fetch request. As a result, the byte multiplexer The data transfer of the channel can be speeded up, and at the same time, the delay of the processing in other devices can be prevented.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing system using an embodiment of a byte multiplexer channel device of the present invention, and FIG. 2 is a timing chart showing an operation sequence during a write operation of the byte multiplexer channel device of FIG. is there.

The byte multiplexer channel device 3 of this embodiment is
It is provided between the main storage device 4 and the input-output control unit 2 and a plurality of input-output devices 1 _a to 1 _m, the memory fetch request flip sending a memory fetch request to the main storage unit 4 at the time of writing system operation 10 and a plurality of bytes (8 bytes in this embodiment) of data sent from the main storage device 4 via the data bus 13 in response to the memory fetch request, and temporarily holds the data. A data buffer 7 that transfers via the output bus 11 for each 1-byte data, a data amount detection register 8 that detects the amount of data in the data buffer 7 and outputs a detection signal to the memory fetch request flip-flop 10. Device number (I / O address) of the I / O device accessed in the previous sequence
And a first input / output address register 5 for holding the input / output address (input via the input bus 12) of the input / output device to be accessed in this sequence. An input / output address comparison circuit that compares the respective input / output addresses held in the first and second input / output address registers 5 and 6 and outputs a detection signal indicating the match / mismatch to the memory fetch request flip-flop 10. 9 and 9.

The main storage device 4 corresponds to each input / output device 1 _a to 1 _m ,
Data to be transferred is stored in different areas, and an area for storing the data is provided. Output control apparatus 2 controls the input and output operation sequence between the byte multiplexer channel unit 3 and the output devices 1 _a to 1 _m, the input-output control unit 2 and between the input and output device 1 _a to 1 _m data transfer is respectively performed through a device interface CH ₁ to CH _m.

 Next, the writing operation of this embodiment will be described.

First, when the byte multiplexer channel device 3, the input / output control device 2, and the input / output devices 1 _a to 1 _m are activated by an input / output instruction from a CPU (not shown), the byte multiplexer channel device 3 is operated in parallel with the CPU. It operates and executes the data transfer process. In this case, first input-output device to data writing is performed among the plurality of input-output devices 1 _a to 1 _m (a 1 _a in this embodiment) to byte multiplexer channel unit 3, for data transfer A request-in signal for requesting a series of sequence processing of is transmitted. When the byte multiplexer channel unit 3 receives this request-in signal, which in response to sending a hold-out signal and the select-out signal, input-output device 1 _a receiving these emit operational in signal. continue,
At time t ₁ , the input / output address is input to the byte multiplexer channel device 3 via the input bus 12 together with the address-in signal, and this address signal is stored in the first input / output address register 5 and correspondingly input. A command out signal is issued indicating that the output address has been received. While the above operation is being performed, the storage of the input / output address held in the first input / output address register 5 in the second series of input / output address registers in the last series of sequence processing is completed. Next, the input / output address comparison circuit 9 compares the input / output addresses held in the first and second input / output address registers 5 and 6 and detects a match / mismatch between them. If there is a mismatch, the memory fetch request flip-flop 10
Is set, and the set memory fetch request flip-flop 10 requests the main memory 4 for data fetch. Then, 8-byte data is output from the main memory device 4 to the byte multiplexer channel device 3 via the data bus 13 and stored in the data buffer 7. Along with this, the value of the data amount detection register 8 is updated, and it is detected that 8 bytes of data are stored in the data buffer 7, and the detection signal is transmitted to the memory fetch request flip-flop 10 and this is detected. Will be reset. Then, at time t ₂ , a service-in signal requesting data writing is issued from the input / output device 1 _a ,
In response to this, at time t ₃ , 1-byte data is read from data buffer 7 and sent out via output bus 11. At time t ₄ , a service-out signal is output from the input / output device.
1 is transmitted to _a, the data input and output device 1 _a at this timing is written. In this way, a series of sequence processing ends. In this state, the data buffer 7, 7 bits of data to be written to the output device 1 _a is stored.

Also in the next sequence, the series of sequence processing described above is repeated. That is, when _a request-in signal is sent again from the input / output device 1a and a series of sequences is started, the input / output addresses of the first and second input / output address registers 5 and 6 by the input / output address comparison circuit 9 are started. In the comparison step, the coincidence of both addresses is detected, and the coincidence detection signal is sent to the memory fetch request flip-flop 10. At this time, since it is confirmed by the detection signal from the data amount detection register 8 that 7 bytes of data remain in the data buffer 7, the memory fetch request flip-flop 10 is set to the reset state without being set. Maintained, no memory fetch request is sent. Thereafter, as described above, a byte of data from the data buffer 7 to the service in signal from the input-output device 1 _a is read out, the data in the service out signal generation timing is written. The input / output address comparison circuit 9 causes the first and second input / output address registers 5, 6
Even if a match of the input / output address of is detected, if no data is stored in the data buffer 7,
The memory fetch request flip-flop 10 is set and the memory fetch request is output.

〔The invention's effect〕

As described above, according to the present invention, in the write operation of the byte multiplexer channel device, when access to the same input / output device continues, a memory fetch request is sent out when transfer data remains in the data buffer. With such a configuration, it is possible to reduce the number of accesses to the main memory device, which makes it possible to speed up data transfer of the byte multiplexer channel device and prevent processing delay in other devices. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing system using an embodiment of a byte multiplexer channel device of the present invention.
The drawing is a timing chart showing the operation sequence during the write operation of the byte multiplexer channel device of FIG. 1 _a to 1 _m …… Input / output device, 2 …… Input / output control device, 3 ……
Byte multiplexer channel device, 4 ... Main memory device, 5 ... First input / output address register, 6 ... Second
I / O address register, 7 ... Data buffer, 8
...... Data amount detection register, 9 ...... Input / output address comparison circuit, 10 ...... Memory fetch request flip-flop, 11
...... Output bus, 12 …… Input bus, 13 …… Data bus, CH
_{1 to} CH _m …… Device interface.

Claims (1)

(57) [Claims] 1. A byte multiplexer channel device in which data transfer between a channel and a main memory device is performed in units of a plurality of bytes, and data transfer between a channel and an input / output device is performed in byte units. A data buffer for temporarily storing a plurality of bytes of data read from the device and sending it to the input / output device for each 1-byte data; and a data buffer to be transferred from the main storage device and stored in the data buffer. Memory fetch request means for sending a memory fetch request to the main storage device, and detecting whether or not data exists in the data buffer, and sending a detection signal to the memory fetch request means. Data amount detecting means, and a byte multiplexer channel device and an input / output device by an input / output instruction from the CPU. When a request to execute processing in a predetermined sequence is input to the byte multiplexer channel device from the I / O device to which data transfer is to be performed, the device address of the I / O device that sent the request. Is stored as an input / output address, and is temporarily held by the first input / output address holding means while the data transfer processing is executed according to the predetermined sequence. Second input / output address holding means for fetching and holding the existing input / output address, and the predetermined sequence is completed, and subsequently, processing is executed in the predetermined sequence from the input / output device to which data transfer is to be performed. A request for input to the byte multiplexer channel device is taken into the first input / output address holding means. The held input / output address is compared with the input / output address held in the second input / output address holding means to detect a match / mismatch between them, and when a match is detected, a match detection signal is output. When the mismatch is detected, the memory fetch request means has respective input / output address comparison means for sending a signal for forcing a memory fetch request to be sent to the memory fetch request means. When the coincidence detection signal from the means is input and it is confirmed by the detection signal from the data amount detection means that the data is held in the data buffer, the memory fetch request is not sent and the input / output address is not sent. Even if the match detection signal from the comparison means is input, if there is no data in the data buffer or the input / output address comparison Is configured to send a memory fetch request to main memory when a signal for forcing a memory fetch request from the memory is input, and when the memory fetch request is not sent, the byte multiplexer channel device is placed in the data buffer. A byte multiplexer channel device characterized by executing a sequence process using held data.