JPS63187349A - Memory device - Google Patents

Abstract

PURPOSE:To shorten a memory access time, by pre-reading a memory address continued at every instruction fetch, operand fetch, and classification of memory access in direct memory access (DMA) transfer. CONSTITUTION:When read access from a processor 1 or another master device is generated, it is decided whether the access is the instruction fetch or the operand fetch of the access, or the DMA transfer by an access classification decision circuit. And when a data whose address coincides with the access address of the master device exists in either data buffer registers 13-16, the content of the data is sent to the master device, and the next data is read out from a memory module by incrementing the values of address counters 5-8, thereby, preparation for the next access is provided. Also, when no address counters 5-8 whose address coincides exist, the address is read out directly from memory modules 17-20, and also, the data of continuous addresses of the installed numbers of memory blocks is block-read from the address, and a corresponding address is set on the address counters 5-8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a storage device for an information processing device, and particularly to a storage device suitable for shortening memory access time.

[Conventional technology]

As a method of shortening the access time of a memory device, for example, as described in the background section of Japanese Patent Application Laid-Open No. 177782/1982, the main memory device and the system interface device are arranged in blocks of a predetermined size. A system was used in which the width of data transfer at one time between them was set to four blocks, and the transfer of the entire block was performed N times.

[Problem that the invention seeks to solve]

The above conventional technology is only used when the data loaded into the backup memory is used only once or only partially because of the waiting time during block read from the main memory to the backup memory or swap-out to the main memory. If not, it cannot be said to be very effective even though expensive high-speed memory is used.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control method that shortens memory access time and is effective even for programs having a structure in which the same routine of the program is not reused within a relatively short cycle.

[Means for solving problems]

The above purpose is to provide a plurality of interleaved memory modules that can be accessed at the same time, and to set up a data buffer register for each memory module. (hereinafter abbreviated as "rDMA") six pillars for transfer are provided, and when a read access from a processor or other master device occurs, the access type control circuit determines whether the access is an instruction fetch, operand fetch, or DMA transfer. The access address from the master device is determined by checking the values of address counters corresponding to the determined access type and the number of address counters corresponding to the number of interleaves indicating the address of the data stored in the register. If there is data matching that in any data buffer register, the contents are sent to the master device, and the address counter is incremented to read the next data from the memory module and prepare for the next access. If a matching address counter does not exist, the address is read directly from the memory module, and the data register VC of the type corresponding to the above memory access is read.
This can be achieved by block reading data from consecutive addresses as many as the number of installed memory blocks from this address, and setting the corresponding address in the address counter.

[Effect]

In the storage device of the present invention, a data buffer register group compatible with instruction fetch is composed of data buffer registers compatible with memory modules, and each data buffer register is provided with a corresponding presettable address counter, The address of the data contained in the data buffer register is set. In addition, if the address of the indulgence access of the instruction fetch from the GRO 6 processor matches any of the data buffer registers mentioned above, the instruction fetch can be read at high speed, which is almost the same as the access time to the data buffer register. Furthermore, since pre-reading of consecutive addresses is performed for each interleaved memory module, the number of memory modules installed, the access time of the memory module multiplied by the number of installed memory modules, is smaller than the cycle time of the processor. If you set this, the instruction address will be continuous unless a branch instruction occurs, so the instruction fetch can be executed at high speed. If the data on the data buffer register becomes unusable due to a branch instruction, the first instruction fetch takes the same amount of time as accessing the memory block, but from then on, the above-mentioned high-speed operation becomes possible.

For operand fetch and DMA transfer,
Since it has a group of data buffer registers, a similar effect occurs for continuous address access.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using FIGS. 1 and 2. FIG. 1 is a diagram showing the configuration of a storage device for implementing the present invention. In the figure, 1 is a processor and 2 is an address register.

3 is a data register, 4 is a control circuit, 5 to 8 are address counters for indicating the addresses of data set in data buffer registers 17 to 2o, 9 to 12 are address comparators, and 13 to 16 are memory modules 17. ~2
Data buffer registers 17 to 20 for temporarily storing data read from 0 are memory modules that can be read simultaneously.

The configuration shown in Figure 1 shows the case where four memory modules are installed, and the address counter, address comparator, and data buffer register are only shown for instruction fetch, and the same applies for operand fetch and DMA transfer. It is omitted because it is.

From the viewpoint of required performance and economy, it is also possible to apply the present invention only to instruction fetch.

FIG. 2 is a time chart for explaining the present invention.

Next, the operation Z according to the present invention will be explained with reference to FIG. 1 and FIG. A signal AS is output.

This address (No. A) is temporarily stored in the address register 2. The control circuit 4 is activated by the address stop AS and checks whether the address counters 5 to 8 are valid. If valid data is not set in the data buffer registers 17 to 20, address counters 5 to 8 are invalid, and the read operation from the memory modules 17 to 20 is performed in response to the access from the a processor 1 described above. Start. Assuming that the address just specified is address “1°,” address counter 6 will be set to 111, and address counter 7 will be set to 1.
2', address counter 8 to 6', address counter 5 to 4°, and memory modules 17 to 20
are read at the same time and the contents of addresses 1 to 4 are set in data buffer registers 16 to 16. Next, the data stored in the data buffer register 14 is transferred to the data register 3, and the data set in the data register 6 is transferred to the processor 1, and the access is completed. Next, the address counter 6 is incremented and the address value becomes '5'', and the memory module 18 prepares the data at address 5.
The operation of reading the data and transferring the data to the data buffer register 14 is started. Next, 2
If we read the address, the data for the 2nd address has already been prepared in the It'L data buffer register 15, so
The data is transferred from the data buffer register 15 to the data register 5, and the operation ends. Next, as described above, the operation of preparing the next data in the data buffer register 15 is started. A time chart of the above operations is shown in FIG. The above operation continues until a branch instruction appears (repeatedly,
This implementation, 7.

For example, the memory access time can be made much faster. When a branch instruction appears, address comparators 9 to 12 no longer match, this is communicated to the control circuit, and the same sequence as the first access is taken.

[Effects of the Invention] According to the present invention, instruction fetch, operand fetch,
Since consecutive memory addresses are pre-read for each type of memory access in DMA transfer, the memory access time can be significantly reduced as long as the memory access addresses for each type are consecutive.

[Brief explanation of the drawing]

Each figure shows an embodiment of the present invention, and FIG. 1 is a configuration diagram of a storage device, and FIG. 2 is a time chart for explaining the operation. Explanation of symbols 1...Processor 2...Address register 6...Data register 4...Control circuits 5-8.
・Address counter ・ 8 ・ 9 to 12 ・ Comparator

Claims (1)

[Claims] 1. In a storage device for an information processing device that has multiple interleaved memory modules that can be accessed simultaneously, read access from a processor or other master device is performed by instruction, fetch, operand fetch, or direct memory access transfer. and a data buffer register group for temporarily storing data read out from the memory module for each of the memory modules corresponding to the plurality of types of access, and the data buffer register group includes means for determining whether the memory is A storage device characterized in that data corresponding to addresses from the current access address to the number of interleaves is read in advance for each type of access.