JPH05143718A - Image processor - Google Patents

Abstract

PURPOSE:To reduce a load concerning the exchange of the communicating data of a host computer. CONSTITUTION:An arithmetic part 3 is composed of a device control part 1 composed of a device control processor 20 to control a memory 4, etc., or manages the exchange of data on buses and a communication data holding circuit 30, data flow control part 2 to control the input of data from a data bus 8 to the arithmetic part 3 or the work memory part 4 or to control the output of data from the arithmetic part 3 or the work memory part 4 to the data bus 8, arithmetic part 3 to execute a signal processing to the inputted image data, work memory part 4 to temporarily store a middle result or to store data required for the arithmetic part 3 to execute the processing operation when processing the input data by this arithmetic part 3, and input/output part 5 to output the image data processed by the arithmetic part 3 to the outside or to supply the image data inputted from the outside to the data bus 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which operates by connecting to an external (host) computer.

[0002]

2. Description of the Related Art Conventionally, in an image processing apparatus in which an arithmetic unit performs signal processing on image data based on processing information supplied from a host computer, a large amount of processing information is transmitted from the host computer to the arithmetic unit side. When supplied, the interpreting speed of the operation unit cannot be met in time, and the host computer has to repeatedly output the same data or transmit the data over time, which causes a problem that data communication takes time. there were.

Further, after sending communication data from the host computer to the arithmetic unit side, it was difficult for the host computer to know the data again. In this case, there is a method of storing the transmitted communication data on the host computer side, but if the data changes due to a trouble on the host side, the data cannot be known. It is an object of the present invention to solve the above problems.

[0004]

The problem to be solved is that data communication takes a long time when a large amount of processing information is supplied. Further, it is difficult for the host computer to know the data again after sending the communication data from the host computer to the arithmetic unit side.

[0005]

According to the present invention, an image processing apparatus adapted to perform signal processing on image data in an arithmetic unit 3 based on processing information supplied from a host computer 6 is provided. Storage means (communication data holding circuit 3) for storing the supplied processing information at an address designated by the host computer.
0) and control means (apparatus control processor 2) for supplying the processing information read from the recording means to the arithmetic section.
0) and the storage means keeps holding data until the processing information is newly supplied from the host computer, and stores the data in the host computer when a read signal is supplied from the host computer. The image processing apparatus is configured to supply the processing information stored at the designated address to the host computer.

[0006]

According to this, since the communication data between the host computer and the arithmetic unit is held in the communication data holding circuit for a predetermined period, the load on the communication of the communication data of the host computer can be reduced.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the image processing apparatus of the present invention will be described with reference to FIG. The image processing apparatus of the present invention controls the arithmetic unit 3, the memory 4, and the like, and controls the exchange of data on the bus. The device control unit 20 includes a device control processor 20 and a communication data holding circuit 30, and a data bus 8. A data flow control unit that controls data input from the calculation unit 3 to the work memory unit 4 or output data from the calculation unit 3 or the work memory unit 4 to the data bus 8; And a work memory for temporarily storing an intermediate result when the calculation unit 3 processes input data, and for storing data necessary for other calculation operations. It is composed of a unit 4 and an input / output unit 5 for outputting the image data processed by the arithmetic unit 3 to the outside and supplying the image data input from the outside to the data bus 8.

The host computer 6 is connected to the device control section 1 via a system bus 9 and is used as an execution control of the image processing device and a program development environment. Then, the program from the external computer 6 is written in a program buffer memory (not shown) in the device control unit 1, and the program read from the program buffer memory is transferred to the data flow control unit 2 via the memory bus 7. It is loaded into the arithmetic unit 3. Further, the work memory unit 4 is accessed from the host computer 1. still,
In the figure, broken lines are control lines and solid lines are data lines.

The arithmetic unit 3 is composed of a large number (eg 72) of processors. The work memory unit 4 is composed of, for example, a memory and an address generation unit, and is used as a one-dimensional to multi-dimensional memory by allocating an address bit. Further, the input / output unit 5 is composed of, for example, a double-buffer type memory and can perform high-speed data input / output, and is adapted to the data rate of an external device connected to the input / output data buses 14 and 15 by an external synchronization system. Input and output can be performed.

The data bus 8 includes, for example, 16 independent bus lines VIR, VIG, VIB, VIA, WIR,
WIG, WIB, WIA, VOR, VOG, VOB, V
It is formed by OA, WOR, WOG, WOB, and WOA, of which eight (VIR, VIG, VIB, VI
A, WIR, WIG, WIB, WIA) is input data to the arithmetic unit 3 (for example, three primary color signals R, G, B and audio signals).
Is used as a bus line for supplying the other eight wires (VOR, VOG,
VOB, VOA, WOR, WOG, WOB, WOA) are bus lines to which output data (for example, processed three primary color signals R, G, B and audio signals) are supplied from the arithmetic unit 3. In addition, four of each of these bus lines (WIR,
WIG, WIB, WIA, WOR, WOG, WOB, W
OA) is connected to the work memory unit 4, and the remaining four lines (VIR, VIG, VIB, VIA, VOR, VOG,
VOB, VOA) is supplied to the input / output unit 5.

Next, referring to FIG. 2, a communication data holding circuit 30 which is provided in the apparatus control and holds the data from the host computer 6 and the data showing the execution status in the arithmetic unit 3 and communication data such as flags will be described with reference to FIG. explain. The communication data holding circuit 30 is composed of a plurality of registers for holding data of any kind. These registers are control registers CR1, CR2, CR3 that hold data from the host computer 6.
And status registers SR1 and SR2 that hold data supplied from the arithmetic unit 3 and the like. The data invention stored in the status registers SR1 and SR2 is read from the host computer 6. Further, the data stored in the control registers CR1, CR2, CR3 can also be read from the host computer 6.

In FIG. 2, the address signal and the read / write signal supplied from the host computer 6 are input to the decoders 31 and 32, respectively. In the decoder 31, registers CR1, CR2, CR3, based on the address signal,
A register selection signal for selecting a desired register from SR1 and SR2 is generated. Also, the decoder 32
In, a write signal and a read signal are generated based on the read / write signal, the write signal is supplied to the control register, and the read signal is supplied to the control register and the status register.

Input data supplied from the host computer is supplied to the control registers CR1, CR2, CR3 and stored in a predetermined control register according to the states of the register selection signal and the write signal. Then, each control register CR1, CR2, CR3
The data stored at is held until new data is supplied and set. The data stored in each of the control registers CR1, CR2, CR3 may be, for example, a part or all of the processors of the arithmetic unit 3 that communicates the start and end of various executions to each other for timing data transfer and the like. A flag, a processor to which debug data is requested, a debug selection signal for activating a debug counter by designating a specific location in the processor, and a map set in a map register of the processor 20 in the control unit 1, respectively. There is data.

Data indicating the execution status supplied from the arithmetic unit 3 and the above flags are stored in the status registers SR1 and SR2 according to the set signal supplied from the arithmetic unit 3. The data stored in the status registers SR1 and SR2 are read according to the register selection signal and the read signal supplied from the decoder 31 and the decoder 32, and are supplied to the host computer 6. The data stored in the status registers SR1 and SR2 are held until data and flags indicating the execution status are newly supplied from the arithmetic unit 3 and set. The data stored in the control registers CR1, CR2, CR3 is also read according to the register selection signal and the read signal supplied from the decoder 31 and the decoder 32 and supplied to the host computer 6.

Next, the control registers CR1 and CR
2, the structure of CR3 will be described with reference to FIG. The register selection signal and the write signal supplied from the decoders 31 and 32 are supplied to the OR circuit 40, and the output signal thereof selectively selects the output signal of the holding register 41 and the data (write data) supplied from the host computer 6. Is supplied to the selector 42 as a selection control signal for the selector 42 to be output to. Further, the register selection signal and the read signal are supplied to the OR circuit 43, and the output signal thereof is used as the output control signal of the register 44 which selectively supplies the output signal of the holding register 41 to the host computer 6, and the register 4
4 is supplied. Then, the output signal of the holding register 41 is supplied to the computing unit 3 and the like as the output signals of the control registers CR1, CR2, CR3.

Next, the structure of the status registers SR1 and SR2 will be described with reference to FIG. Decoder 31, 3
The register selection signal and the read signal supplied from 2 are supplied to the OR circuit 50, and the output signal is supplied to the register 51 as a storage control signal of the register 51 that stores the data supplied from the arithmetic unit 3. The output signal of the register 51 is the status registers SR1 and SR2.
Is output to the host computer 6.

Next, the operation of setting the data from the host computer 6 in the communication data holding circuit 30 will be described. First, the host computer 6 supplies an address signal to the decoder 31 to select a desired register among the control registers CR1, CR2, CR3. For example, the address 00 is output when the control register CR1 is selected, the address 01 is output when the control register CR2 is selected, and the address 0 is output when the control register CR3 is selected.
2 is output. The decoder 31 sets only the register selection signal supplied to the control register designated by the input address to the low level. Further, the host computer 6 supplies, for example, 10 as a read / write signal to the decoder 32, so that the decoder 32 outputs a low-level write signal. The control register selected by the register selection signal output from the decoder 31 stores and holds the data from the host computer according to the write signal output from the decoder 32. Then, the data newly set in the control register is supplied to the arithmetic unit 3.

Next, the operation of setting the data from the arithmetic unit 3 in the status registers SR1 and SR2 will be described. Data and flags indicating the execution status output from the arithmetic unit 3 are stored and held in the status registers SR1 and SR2 in response to the set signal supplied from the arithmetic unit 3.
At this time, the data stored and held in the status registers SR1 and SR2 are not supplied to the host computer 6 unless a read signal is supplied from the host computer 6. Then, the control registers CR1 and C
R2, CR3 and status registers SR1, SR2
The data stored in is selectively supplied to the host computer 6 according to the address signal and the read / write signal supplied from the host computer 6.

The communication data holding circuit is shown in FIG.
In addition to the configuration shown in FIG. 5, the communication data holding circuit having the configuration shown in FIG. 5 may be applied. The communication data holding circuit shown in FIG. 5 uses a 2-port memory instead of the register, and the control memory (C-Memory) corresponds to the register shown in FIG. 2 and the status memory (S-Mem).
ory) corresponds to the status register shown in FIG.
In the communication data holding circuit having the configuration shown in FIG. 5, no address decoder is needed.

According to the above-described image processing apparatus of the present invention, since the communication data between the host computer and the arithmetic unit is held in the communication data holding circuit for a predetermined period, the load on the communication of the communication data of the host computer is reduced. it can. This device is particularly effective in the case of status data.

Further, since the host computer can read the communication data transmitted from the host computer to the image processing apparatus from the communication data holding circuit, the host computer can confirm that the data has been correctly transmitted from the host computer to the image processing apparatus. You can check. Further, it is not necessary for the host computer side to store the communication data sent immediately before.

[0022]

According to the present invention, since the communication data between the host computer and the arithmetic unit is held in the communication data holding circuit for a predetermined period, the load on the communication of the communication data of the host computer can be reduced. ..

[Brief description of drawings]

FIG. 1 is a block diagram of an example of an image processing apparatus according to the present invention.

FIG. 2 is a block diagram of the communication data holding circuit.

FIG. 3 is a block diagram of a control register.

FIG. 4 is a block diagram of a status register.

FIG. 5 is a block diagram of a communication data holding circuit (modification).

[Explanation of symbols]

 1 Device Control Section 2 Data Flow Control Section 3 Computing Section 4 Work Memory Section 5 Input / Output Section 6 Host Computer 7 Memory Bus 8 Data Bus 9 System Bus 10, 11, 12, 13 Control Line 14, 15 Input Output data 16, 17, 18 Signal line 20 Device control processor 30 Communication data holding circuit

Claims (1)

[Claims] 1. An image processing apparatus configured to perform signal processing on image data in an arithmetic unit based on processing information supplied from a host computer, wherein the processing information supplied from the host computer is stored in the host computer. And a control means for supplying the processing information read from the recording means to the arithmetic unit, wherein the storage means newly stores the processing information from the host computer. Data is held for a period until it is supplied, and the processing information stored at the address designated by the host computer is supplied to the host computer when a read signal is supplied from the host computer. An image processing device characterized in that