JPS5714922A - Storage device - Google Patents

Storage device

Info

Publication number
JPS5714922A
JPS5714922A JP8923280A JP8923280A JPS5714922A JP S5714922 A JPS5714922 A JP S5714922A JP 8923280 A JP8923280 A JP 8923280A JP 8923280 A JP8923280 A JP 8923280A JP S5714922 A JPS5714922 A JP S5714922A
Authority
JP
Japan
Prior art keywords
selector
reception
register
storage device
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8923280A
Other languages
Japanese (ja)
Other versions
JPS6346864B2 (en
Inventor
Junichi Takuri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8923280A priority Critical patent/JPS5714922A/en
Publication of JPS5714922A publication Critical patent/JPS5714922A/en
Publication of JPS6346864B2 publication Critical patent/JPS6346864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To ensure connection of a storage device to a number of CPUs of different machine cycles without any change of the hardware, by giving a logic degree of freedom to the time relation of the interface system. CONSTITUTION:A storage device MS works synchronously with the basic clock tO-3. The MS incorporates a clock selector 8 and a constitution controlling register 7. The selector 8 selects both the transmission and reception clocks ti and tj of the interface signal out of the basic clock to supply them to interface reception and transmission latches 2 and 3 respectively. The logic clock selection of the selector 8 is controlled by the register 7. Plural pairs of these registers and selectors are prepared to the input/output interface signal in order to ensure a logically free selection of both the reception and transmission clocks of the interface signal through writing to each register 7.
JP8923280A 1980-07-02 1980-07-02 Storage device Granted JPS5714922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8923280A JPS5714922A (en) 1980-07-02 1980-07-02 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8923280A JPS5714922A (en) 1980-07-02 1980-07-02 Storage device

Publications (2)

Publication Number Publication Date
JPS5714922A true JPS5714922A (en) 1982-01-26
JPS6346864B2 JPS6346864B2 (en) 1988-09-19

Family

ID=13964996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8923280A Granted JPS5714922A (en) 1980-07-02 1980-07-02 Storage device

Country Status (1)

Country Link
JP (1) JPS5714922A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054243A2 (en) * 1980-12-17 1982-06-23 Hitachi, Ltd. Memory controlling apparatus
JPS59136829A (en) * 1982-12-23 1984-08-06 シ−メンス，アクチエンゲゼルシヤフト Circuit module
JPS60122454A (en) * 1983-12-07 1985-06-29 Hitachi Ltd Data transfer control system
JPS60192041U (en) * 1984-05-31 1985-12-20 富士通株式会社 data transfer control device
EP0283628A2 (en) * 1987-02-24 1988-09-28 Digital Equipment Corporation Bus interface circuit for digital data processor
US6182184B1 (en) 1990-04-18 2001-01-30 Rambus Inc. Method of operating a memory device having a variable data input length
US6405296B1 (en) 1996-05-07 2002-06-11 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4933421A (en) * 1972-07-30 1974-03-27
JPS5369556A (en) * 1976-12-03 1978-06-21 Fujitsu Ltd Timing selecting system
JPS5461848A (en) * 1977-10-27 1979-05-18 Mitsubishi Electric Corp Bus signal controller of computer
JPS55118398U (en) * 1979-02-13 1980-08-21

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4933421A (en) * 1972-07-30 1974-03-27
JPS5369556A (en) * 1976-12-03 1978-06-21 Fujitsu Ltd Timing selecting system
JPS5461848A (en) * 1977-10-27 1979-05-18 Mitsubishi Electric Corp Bus signal controller of computer
JPS55118398U (en) * 1979-02-13 1980-08-21

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054243A2 (en) * 1980-12-17 1982-06-23 Hitachi, Ltd. Memory controlling apparatus
JPS59136829A (en) * 1982-12-23 1984-08-06 シ−メンス，アクチエンゲゼルシヤフト Circuit module
JPS60122454A (en) * 1983-12-07 1985-06-29 Hitachi Ltd Data transfer control system
JPS60192041U (en) * 1984-05-31 1985-12-20 富士通株式会社 data transfer control device
EP0283628A2 (en) * 1987-02-24 1988-09-28 Digital Equipment Corporation Bus interface circuit for digital data processor
US6260097B1 (en) 1990-04-18 2001-07-10 Rambus Method and apparatus for controlling a synchronous memory device
US6182184B1 (en) 1990-04-18 2001-01-30 Rambus Inc. Method of operating a memory device having a variable data input length
US6266285B1 (en) 1990-04-18 2001-07-24 Rambus Inc. Method of operating a memory device having write latency
US6314051B1 (en) 1990-04-18 2001-11-06 Rambus Inc. Memory device having write latency
US6378020B2 (en) 1990-04-18 2002-04-23 Rambus Inc. System having double data transfer rate and intergrated circuit therefor
US6415339B1 (en) 1990-04-18 2002-07-02 Rambus Inc. Memory device having a plurality of programmable internal registers and a delay time register
US6570814B2 (en) 1990-04-18 2003-05-27 Rambus Inc. Integrated circuit device which outputs data after a latency period transpires
US6584037B2 (en) 1990-04-18 2003-06-24 Rambus Inc Memory device which samples data after an amount of time transpires
US6405296B1 (en) 1996-05-07 2002-06-11 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory

Also Published As

Publication number Publication date
JPS6346864B2 (en) 1988-09-19

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