JPS5461848A - Bus signal controller of computer - Google Patents

Bus signal controller of computer

Info

Publication number
JPS5461848A
JPS5461848A JP12928477A JP12928477A JPS5461848A JP S5461848 A JPS5461848 A JP S5461848A JP 12928477 A JP12928477 A JP 12928477A JP 12928477 A JP12928477 A JP 12928477A JP S5461848 A JPS5461848 A JP S5461848A
Authority
JP
Japan
Prior art keywords
speed
low
circuit
timing
program processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12928477A
Other languages
Japanese (ja)
Inventor
Tetsuo Yano
Masaharu Nishikawa
Moichi Hirasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12928477A priority Critical patent/JPS5461848A/en
Publication of JPS5461848A publication Critical patent/JPS5461848A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To improve a functional speed on the whole, by providing a timing regulator circuit which prevents address signals from mixing together by separating a high-speed program processing part from a low-speed program processing part and makes access to either high-speed or low-speed program judging from information on assigned address.
CONSTITUTION: This bus controller 8 of the computer is provided with high-speed program processing parts 9a to 9c, and low-speed program processing parts 10a to 10c, which operate at a high or low speed, connected to signal bus 12 exchanging input-output signals connected to controller 8. Controller 8 in this constitution is provided with main logic circuit 16, clock signal generating circuits 17a and 17b which generate high-speed or low-speed timing, and logic circuit 21 which makes an alternation between circuits 17a and 17b by being supplied with address signal 18 from circuit 16 and control signal 20 inputted to or outputted from circuit 16. Further, timing generating circuit 22 is provided which generates clock timing switched to either high or low speed by circuit 21, thereby controlling processing parts 9a to 9c, and 10a to 10c.
COPYRIGHT: (C)1979,JPO&Japio
JP12928477A 1977-10-27 1977-10-27 Bus signal controller of computer Pending JPS5461848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12928477A JPS5461848A (en) 1977-10-27 1977-10-27 Bus signal controller of computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12928477A JPS5461848A (en) 1977-10-27 1977-10-27 Bus signal controller of computer

Publications (1)

Publication Number Publication Date
JPS5461848A true JPS5461848A (en) 1979-05-18

Family

ID=15005768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12928477A Pending JPS5461848A (en) 1977-10-27 1977-10-27 Bus signal controller of computer

Country Status (1)

Country Link
JP (1) JPS5461848A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5714922A (en) * 1980-07-02 1982-01-26 Hitachi Ltd Storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5714922A (en) * 1980-07-02 1982-01-26 Hitachi Ltd Storage device
JPS6346864B2 (en) * 1980-07-02 1988-09-19 Hitachi Ltd

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