JPS5693434A - Counter - Google Patents
CounterInfo
- Publication number
- JPS5693434A JPS5693434A JP17066679A JP17066679A JPS5693434A JP S5693434 A JPS5693434 A JP S5693434A JP 17066679 A JP17066679 A JP 17066679A JP 17066679 A JP17066679 A JP 17066679A JP S5693434 A JPS5693434 A JP S5693434A
- Authority
- JP
- Japan
- Prior art keywords
- selectors
- select
- signal
- operated
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318522—Test of Sequential circuits
- G01R31/318527—Test of counters
Abstract
PURPOSE:To perform the function test of the counter circuit easily with a short test pattern, by using selectors to operate the counter circuit as a shift register at the test time. CONSTITUTION:Select signals are so supplied that selectors 21, 22, and 23 select outputs Q1, Q2 and Q3 respectively and selectors 31, 32, and 33 select input signal IN. Outputs Q1, Q2, and Q3 are given to input terminals D2, D3, and D4, and input signal IN is applied to clock terminals phi2, phi3, and phi4. Here, D type FF11 is operated as a one-stage binary counter. D type FFs 12 and 13 are operated as a shift register which delays the output of FF11 successively with signal (a) as the clock signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17066679A JPS5693434A (en) | 1979-12-27 | 1979-12-27 | Counter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17066679A JPS5693434A (en) | 1979-12-27 | 1979-12-27 | Counter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5693434A true JPS5693434A (en) | 1981-07-29 |
Family
ID=15909113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17066679A Pending JPS5693434A (en) | 1979-12-27 | 1979-12-27 | Counter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5693434A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60193474A (en) * | 1984-02-21 | 1985-10-01 | ミエツチスラーフ ミロースキ | Digital type repeating rate averaging circuit |
US5740219A (en) * | 1996-12-03 | 1998-04-14 | Vlsi Technology, Inc. | Digital counter test circuit |
-
1979
- 1979-12-27 JP JP17066679A patent/JPS5693434A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60193474A (en) * | 1984-02-21 | 1985-10-01 | ミエツチスラーフ ミロースキ | Digital type repeating rate averaging circuit |
JPH0510108B2 (en) * | 1984-02-21 | 1993-02-08 | Mirowski Mieczyslaw | |
US5740219A (en) * | 1996-12-03 | 1998-04-14 | Vlsi Technology, Inc. | Digital counter test circuit |
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