JPS5455141A - Diagnosing shift circuit - Google Patents

Diagnosing shift circuit

Info

Publication number
JPS5455141A
JPS5455141A JP12209777A JP12209777A JPS5455141A JP S5455141 A JPS5455141 A JP S5455141A JP 12209777 A JP12209777 A JP 12209777A JP 12209777 A JP12209777 A JP 12209777A JP S5455141 A JPS5455141 A JP S5455141A
Authority
JP
Japan
Prior art keywords
flops
flip
shift
logical
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12209777A
Other languages
Japanese (ja)
Inventor
Yasunori Ouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12209777A priority Critical patent/JPS5455141A/en
Publication of JPS5455141A publication Critical patent/JPS5455141A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To enable a circuit to cope with a fault of either logical-value-0 fixation or logical-value-1 fixiation, by inverting the shift output of a shift register responding to an external control signal.
CONSTITUTION: Exclusive-OR circuit 22 is provided which receives the shift output of register 5 as one input and common control input 7 as the other. When control input 7 has logical value "1", shift outputs of flip-flops A3 and B3 are inverted by exclusive-OR circuits 21 and 22 respectively and then transmitted to flip-flops B1 and C1. When control input 7 has logical value "0", on the other hand, shift outputs of flip-flops A3 and B3 are not inverted by exclusive-OR circuits 21 and 22, but transmitted directly to flip-flops B1 and C1 rspectively
COPYRIGHT: (C)1979,JPO&Japio
JP12209777A 1977-10-11 1977-10-11 Diagnosing shift circuit Pending JPS5455141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12209777A JPS5455141A (en) 1977-10-11 1977-10-11 Diagnosing shift circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12209777A JPS5455141A (en) 1977-10-11 1977-10-11 Diagnosing shift circuit

Publications (1)

Publication Number Publication Date
JPS5455141A true JPS5455141A (en) 1979-05-02

Family

ID=14827566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12209777A Pending JPS5455141A (en) 1977-10-11 1977-10-11 Diagnosing shift circuit

Country Status (1)

Country Link
JP (1) JPS5455141A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5618766A (en) * 1979-07-26 1981-02-21 Fujitsu Ltd Testing apparatus for logic circuit
JPH01308981A (en) * 1988-06-08 1989-12-13 Nec Corp Integrated circuit
JPH0519017A (en) * 1991-07-10 1993-01-26 Fujitsu Ltd Logic circuit tester
US8356217B2 (en) 2009-06-29 2013-01-15 Fujitsu Limited Storage circuit, integrated circuit, and scanning method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5618766A (en) * 1979-07-26 1981-02-21 Fujitsu Ltd Testing apparatus for logic circuit
JPH0323871B2 (en) * 1979-07-26 1991-03-29 Fujitsu Ltd
JPH01308981A (en) * 1988-06-08 1989-12-13 Nec Corp Integrated circuit
JPH0519017A (en) * 1991-07-10 1993-01-26 Fujitsu Ltd Logic circuit tester
US8356217B2 (en) 2009-06-29 2013-01-15 Fujitsu Limited Storage circuit, integrated circuit, and scanning method

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