JPS561356A - Logical-signal detection circuit - Google Patents

Logical-signal detection circuit

Info

Publication number
JPS561356A
JPS561356A JP7677279A JP7677279A JPS561356A JP S561356 A JPS561356 A JP S561356A JP 7677279 A JP7677279 A JP 7677279A JP 7677279 A JP7677279 A JP 7677279A JP S561356 A JPS561356 A JP S561356A
Authority
JP
Japan
Prior art keywords
glitch
logical
circuit
latch
logical data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7677279A
Other languages
Japanese (ja)
Inventor
Shuichi Isoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP7677279A priority Critical patent/JPS561356A/en
Publication of JPS561356A publication Critical patent/JPS561356A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To reduce the number of memories needed for a logical-signal detection circuit and to simplify the circuit constitution, by permitting three outputs, that is, logical data, glitch, and latch ouputs to be used according to the need so that necessary functions can be selected.
CONSTITUTION: A glitch detector 7, which comprises flip-flops Q2, Q3, Q4, Q5, and Q10, exclusive "or" circuits Q6 and Q7, and an "and" circuit Q8, can obtain a positive signal when there are a positive edge and a negative edge between clocks more than once at the same time, that is, there is a glitch. A flip-flop Q9 samples an input signal at the positive edge of the clock. An exclusive "or" circuit Q11 inverts the logical data output when there is a glitch, to make a latch output. Thus, the three outputs, that is, logical data, glitch, and latch ouputs can be freely used.
COPYRIGHT: (C)1981,JPO&Japio
JP7677279A 1979-06-20 1979-06-20 Logical-signal detection circuit Pending JPS561356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7677279A JPS561356A (en) 1979-06-20 1979-06-20 Logical-signal detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7677279A JPS561356A (en) 1979-06-20 1979-06-20 Logical-signal detection circuit

Publications (1)

Publication Number Publication Date
JPS561356A true JPS561356A (en) 1981-01-09

Family

ID=13614870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7677279A Pending JPS561356A (en) 1979-06-20 1979-06-20 Logical-signal detection circuit

Country Status (1)

Country Link
JP (1) JPS561356A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164531A (en) * 1980-05-21 1981-12-17 Hitachi Ltd Manufacture of semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164531A (en) * 1980-05-21 1981-12-17 Hitachi Ltd Manufacture of semiconductor

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