JPS5533256A - Error detection control system - Google Patents

Error detection control system

Info

Publication number
JPS5533256A
JPS5533256A JP10608678A JP10608678A JPS5533256A JP S5533256 A JPS5533256 A JP S5533256A JP 10608678 A JP10608678 A JP 10608678A JP 10608678 A JP10608678 A JP 10608678A JP S5533256 A JPS5533256 A JP S5533256A
Authority
JP
Japan
Prior art keywords
error
flip
units
flops
error detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10608678A
Other languages
Japanese (ja)
Inventor
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10608678A priority Critical patent/JPS5533256A/en
Publication of JPS5533256A publication Critical patent/JPS5533256A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To detect an error occurring first by providing machine check control units with flip-flops and also by permitting an error wave even after one machine clock.
CONSTITUTION: If unit 1-0 gets of order, error detection circuit 3-0 sets error flip- flop 4-0 and error holding flip-flop 9 is also set synchronizing with machine clocks. As a result, an error freeze signal is distributed to respective units 1-0, 1-1, 1-2.... Namely, respective flip-flops 4-0, 4-1 and 4-2 in units 1-0, 1-1 and 1-2 are inhibited from being set continuously. Units 1-0, 1-1, etc., are provided with circuits 10 and 11 which inhibits the continuous setting of error flip-flops 4-0 and 4-1.
COPYRIGHT: (C)1980,JPO&Japio
JP10608678A 1978-08-30 1978-08-30 Error detection control system Pending JPS5533256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10608678A JPS5533256A (en) 1978-08-30 1978-08-30 Error detection control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10608678A JPS5533256A (en) 1978-08-30 1978-08-30 Error detection control system

Publications (1)

Publication Number Publication Date
JPS5533256A true JPS5533256A (en) 1980-03-08

Family

ID=14424735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10608678A Pending JPS5533256A (en) 1978-08-30 1978-08-30 Error detection control system

Country Status (1)

Country Link
JP (1) JPS5533256A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854866U (en) * 1981-10-07 1983-04-14 美津濃株式会社 shuttlecock

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5854866U (en) * 1981-10-07 1983-04-14 美津濃株式会社 shuttlecock

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