JPS5488748A - Error detection system - Google Patents
Error detection systemInfo
- Publication number
- JPS5488748A JPS5488748A JP15715977A JP15715977A JPS5488748A JP S5488748 A JPS5488748 A JP S5488748A JP 15715977 A JP15715977 A JP 15715977A JP 15715977 A JP15715977 A JP 15715977A JP S5488748 A JPS5488748 A JP S5488748A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- registers
- stage
- operation circuit
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Retry When Errors Occur (AREA)
Abstract
PURPOSE: To detect intermittent error of operation circuit with a set of operation circuit, by performing the same operation in a plurality number in the operation circuit, setting the result of operation to a plurality of registers, and performing subtraction among registers.
CONSTITUTION: The stage forming circuit 23 continuously produces the instruction readout signal IF24, first and second signals 25 and 26 representing the operand readout stage, and operation stage signal 27, and also develops the stage signals 32 to 34 based on the basic clock signal 28. Further, based on the signals 32 to 34, the operation circuit 17 performs the same operation in a plural number of times, the result of operation is set to a plurality of operation registers 14 and 15, the subtraction between the registers 14 and 15 is made with the operation circuit 17, the result is detected with the zero detection circuit 37, and intermittent error caused by the operation circuit is detected.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15715977A JPS5488748A (en) | 1977-12-26 | 1977-12-26 | Error detection system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15715977A JPS5488748A (en) | 1977-12-26 | 1977-12-26 | Error detection system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5488748A true JPS5488748A (en) | 1979-07-14 |
Family
ID=15643463
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15715977A Pending JPS5488748A (en) | 1977-12-26 | 1977-12-26 | Error detection system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5488748A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002527820A (en) * | 1998-10-12 | 2002-08-27 | センタ・ナショナル・デチュード・スパティアレ | Processing procedure and memory access monitoring device for electronic system subject to transient error constraint |
-
1977
- 1977-12-26 JP JP15715977A patent/JPS5488748A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002527820A (en) * | 1998-10-12 | 2002-08-27 | センタ・ナショナル・デチュード・スパティアレ | Processing procedure and memory access monitoring device for electronic system subject to transient error constraint |
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