JPS5488168A - Phase shift detector - Google Patents

Phase shift detector

Info

Publication number
JPS5488168A
JPS5488168A JP15553577A JP15553577A JPS5488168A JP S5488168 A JPS5488168 A JP S5488168A JP 15553577 A JP15553577 A JP 15553577A JP 15553577 A JP15553577 A JP 15553577A JP S5488168 A JPS5488168 A JP S5488168A
Authority
JP
Japan
Prior art keywords
circuit
clock
signal
clock signal
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15553577A
Other languages
Japanese (ja)
Inventor
Seiichi Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15553577A priority Critical patent/JPS5488168A/en
Publication of JPS5488168A publication Critical patent/JPS5488168A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

PURPOSE: To enable the use in a high frequency range to be made by having a latch circuit which checks and holds clocks by using the delay signal of the clocks as latch clock.
CONSTITUTION: A PLL circuit 1 generates a data differentiation signal 21 and the clock signal 24 synchronized to input data 20. The PLL clock singal 24 operates a flip-flop circuit 3 to generate the signals 25, 26. The PLL clock signal 24 is sent to a delay circuit 17 to generate a delay clock signal 40. This clock signal 40 is used as the sample clock of a latch circuit 18. The latch circuit 18 checks and holds the condition of the output 39 of an OR circuit 16 being logic 1 at the rise of the sample clock.
COPYRIGHT: (C)1979,JPO&Japio
JP15553577A 1977-12-26 1977-12-26 Phase shift detector Pending JPS5488168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15553577A JPS5488168A (en) 1977-12-26 1977-12-26 Phase shift detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15553577A JPS5488168A (en) 1977-12-26 1977-12-26 Phase shift detector

Publications (1)

Publication Number Publication Date
JPS5488168A true JPS5488168A (en) 1979-07-13

Family

ID=15608180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15553577A Pending JPS5488168A (en) 1977-12-26 1977-12-26 Phase shift detector

Country Status (1)

Country Link
JP (1) JPS5488168A (en)

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