JPH01144287A - Data memory - Google Patents

Abstract

PURPOSE:To shorten a processing time by providing a signal transmission control circuit between the memories of 2-terminal memory device, connecting the memories and the signal transmission control circuit with a memory signal line, and transmitting the stored data of the memories between the mutual memories based on a clock signal, etc. CONSTITUTION:A signal transmission control circuit 16 is provided between the memories 11 of the 2-terminal memory device, the memories 11 and its signal transmission control circuit 16 are connected with a memory signal line 17, and the stored data of the memories 11 are transmitted between the mutual memories 11 based on a clock signal 18, etc. Consequently, the data in a memory 11 can be directly transmitted to another memory 11 next to the former memory 11 regardless of the sequence synchronously with the clock signal inputted from the external part of the 2-terminal memory device through the clock signal line 18. Thus, the processing time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data storage device, and more particularly to a two-terminal storage device that can read and write data stored in a memory independently from two terminals of the memory. It is something.

[Conventional technology]

FIG. 4 shows a conventional data storage device, in which 1
1 is a memory that has two data input/output terminals and stores data; 12a is a memory control circuit that controls read/write of data in the memory from one terminal of the memory 11; and 12b is a memory for the other terminal. Memory control circuit, 13
Access signal lines 1 a and 13b transmit access H control instructions to the memory control circuits 12a and 12b, respectively.
4a and 14b are memory control circuits 12a and 112b, respectively.
Read/write signal lines 15a and 15b are data signal lines that transmit data written to the memory IJ 11 or data read from the memory 11 via the memory control circuits 12a and 12b, respectively. be. In addition, FIG. 4 shows a data storage device having a total of four two-terminal storage devices, two columns each in the vertical and horizontal directions.

Next, the operation will be explained.

In FIG. 4, the memory control circuit 12a connected to one terminal of the two terminals connected to the memory 11 will be described. The operation of the memory control circuit 12b for the other terminal is completely similar.

First, the operation of reading data stored in the memory 11 will be explained.

Access signal line 13a connected to memory control circuit 12a
and read/write signal '4% 14 a in this example,
It shall be controlled as shown in the table below.

Therefore, when reading data from the memory 11, a control signal is input to the two-terminal storage device so that the access signal 'a 13 a -1 read/write signal line 14a-0 is generated.

The memory control circuit 12a reads data in the memory 11 and outputs it to the data signal line 15a.

Next is the data signal! The operation of storing data 15a in memory 11 will be explained.

Input the control signals to the two-terminal storage device as follows according to the table above.

Access signal line 13a-1 Read/write signal line t4a-1 The memory control circuit 12a writes the data transmitted from the data signal line 15a into the memory 11.

[Problem that the invention seeks to solve]

Conventional data storage devices are configured as described above, so when moving stored data sequentially to an adjacent memory, the stored data is read out of the two-terminal storage device by read access, and then transferred to another memory. There is a problem in that the memory of the two-terminal storage device at the location must be rewritten by write access, and the processing takes a lot of time.

This invention was made to solve the above-mentioned problems, and according to a control signal from outside the two-terminal storage device,
It is an object of the present invention to provide a data storage device that can sequentially and directly transfer stored data in the memory of a two-terminal storage device to the memory of an adjacent two-terminal storage device.

[Means for solving problems]

In the data storage device according to the present invention, a signal transmission control circuit is provided between the memories of the two-terminal storage device, the memory and the one-word transmission control circuit are connected by a memory signal line, and data stored in the memory is transmitted by a clock signal. The information is transmitted between memories based on the following information.

[Effect]

In this invention, a signal transmission control circuit is provided between the memories of a two-child storage device, the memories and the signal transmission control circuit are connected by a memory signal line, and data stored in the memories is transferred between the memories based on a clock signal or the like. Since the data is transmitted between the two terminals, data in the memory can be directly transmitted sequentially to the adjacent memory in synchronization with a clock signal input from outside the two-terminal storage device via the clock signal line.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a data storage device having a two-terminal storage device according to an embodiment of the present invention.
2a is a memory control circuit that controls reading and writing of data in the memory 11 from one terminal of the memory 11; 12b;
is also a memory control circuit for another terminal, ! 3a, 13
Access signal lines 14a and 14b transmit access control instructions to the memory control circuits j2 and 2.12b, respectively;
Reference numerals 14b are read/write signal lines for transmitting read or write instructions to the dry control circuits 12a and 12b, respectively.

Further, 15a and 15b are memory control circuits 12a and 15b, respectively.
, 1'2b, a data signal line 16 is provided between two two-terminal storage devices to transmit data written to the memory 11 or data read from the memory, and is used to transmit data in the memory between the memories. 17 is a memory signal line for transmitting data in the memory between the memory 11 and the signal transmission control circuit 16; 18 is a clock signal for transmitting signal transmission timing to the signal transmission control circuit 16; It is a line.

Next, the operation will be explained.

In FIG. 1, the operations of the two memory control circuits connected to the memory 11 are the same as in the conventional device, and the memory control circuit 12a on the side of one of the two terminals will be described.

First, the operation of reading data stored in the memory 11 will be explained.

In this example, the access signal line 13a and read/write signal line 14a connected to the memory control circuit 12a are controlled as shown in the following table.

Therefore, when reading data from the memory 11, the following control signal is input to the two-terminal storage device.

Access signal line 13a-1 Read/write signal line 14a-0 The memory control circuit I2a reads data in the memory 11 and outputs it to the data signal line 15a.

Next, the operation of storing the data of the data signal 'a15a in the memory 11 will be explained.

According to the table above, the following control signals are input to the two-terminal storage device.

Access signal line 13a-1 Read/write signal line 14a-1 The memory control circuit 12a writes the data transmitted from the data signal vA15a into the memory 11.

The other terminal operates similarly via the memory control circuit 12b.

Next, the operation of sequentially transmitting data in the memory 11 will be explained.

The signal transmission control circuit 16 operates as follows in this embodiment.

First, when the clock signal line 18 is controlled to the 0 (low) state, data in the memory 11 at the previous stage of the signal transfer control circuit 16 is transferred to the signal transfer control circuit 16 via the memory signal line 17.
The signal transmission control circuit 16 holds the memory contents according to the table above.

Next is the clock signal! 18 is controlled to the 1 (high) state, the data in the previous stage memory 11 held by the signal transmission control circuit 16 is transmitted to the subsequent stage memory 11 via the memory signal line 17 and is held.

As described above, the contents of the memory 11 are sequentially transmitted to the memory 11 on the right in FIG.

In this embodiment, the clock signal N
Signal transmission control circuit 16 for all circuits with one lA18
Although one type of signal is simultaneously supplied to the clock signal lines, there may be a plurality of these clock signal lines.

FIG. 2 shows the circuit configuration of a data storage device when there are two clock signal lines. In the figure, 38a is a clock signal line, 38b is another clock signal line, and the rest are the above-mentioned clock signal lines. The configuration is the same as that of the first embodiment.

Next, the operation of the memory control circuit in such a configuration will be explained.

Since the read/write operation for data in the memory 11 from the two terminals is the same as that in FIG. 1, it will be omitted, and only the control of data transmission between the memories 11 will be explained. The two clock signal lines 38a and 38b can be controlled independently. The clock signal line 38a transmits the same control signal as in FIG. 1, but data is transmitted between memories using the clock signal line 3 of the signal transmission control circuit 16 in FIG.
Only the upper two circuits are connected to 8a.

In addition to the effects of the first embodiment, this embodiment can control the transmission of data in the memory 11 by limiting it to a portion.

Furthermore, in the first and second embodiments described above, as shown in FIGS. 1 and 2, the signal transmission control circuit 16 is controlled only by the clock signal line 18 or 38a, 38b. In addition to the signal line, a direction control signal line for data transmission may be provided.

FIG. 3 shows a circuit configuration of a data storage device when there is a data transmission direction control signal line in addition to a clock signal line. This is a data transmission direction control signal line that controls the direction of data transmission via the signal line 17, and the rest is the same as in the first embodiment.

Next, the operation of the memory control circuit in such a configuration will be explained.

The read/write operation for data in the memory 11 from the two terminals is the same as in FIG. 1, so it will be omitted.
The data transmission control between the two will be explained.

In this embodiment, the signal transmission control circuit 46 operates as shown in the following table.

First, in the case of the data transmission direction control signal wA49-0 (low), the operation is the same as that shown in FIG.

Next, in the case of the data transmission direction control signal line 49-1 (high), the data flow in FIG. 1 is reversed.

That is, when the clock signal line 18 is controlled to the O (low) state, the data in the right memory 11 becomes the memory signal [17
to the left-hand signaling control circuit 46, which maintains the memory contents according to the table above.

Next, when the clock signal line 18 is controlled to the 1 (high) state, the data in the right memory 11 held by the signal transmission control circuit 46 is transmitted to the left memory 11 via the memory signal line 17. , is retained.

In addition to the effects of the first embodiment, this embodiment has the advantage that data in the memory 11 can be freely transmitted in either the left or right direction.

〔Effect of the invention〕

As described above, according to the present invention, a signal transmission control circuit is provided between the memories of a two-terminal storage device, the memory and the signal transmission control circuit are connected by a memory signal line, and data stored in the memory is converted into a clock signal or the like. Since data is directly transferred between memories based on the data storage system, data in a two-terminal storage device can be moved quickly and arbitrarily to the memory of another two-terminal storage device without having to read the data out of the device. Can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data storage device having a two-terminal storage device according to a first embodiment of the invention, and FIGS. 2 and 3 are data storage devices according to second and third embodiments of the invention, respectively. FIG. 4 is a block diagram showing an example of a conventional data storage device. 11...Memory, 12a, 12b...Memory control circuit, 13a, 13b-Access signal line, 14a. 14b...Read/write signal line, 15a, 15b...
・Data signal line, 16... Signal transmission control circuit, 17.
...Memory signal line, 18.38a, 38b...Clock signal line, 46...Signal transmission control circuit, 49...Data transmission direction system? I signal line. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A memory having two terminals for data input/output,
In a data storage device having a plurality of two-terminal storage devices each including two memory control circuits that independently control read/write of data from each of the terminals, What is claimed is: 1. A data storage device comprising a signal transmission control circuit which is connected to the memory and transmits data stored in the memories between the memories based on a transmission control signal. (2) The data storage device according to claim 1, wherein the signal transmission control circuit transmits data stored in the preceding memory to the succeeding memory based on a clock signal. (3) The signal transmission control circuit is characterized in that it transmits the data stored in the memory from the preceding memory to the subsequent memory, or vice versa, based on a clock signal and a data transmission direction control signal. A data storage device according to claim 1. (4) According to any one of claims 1 to 3, wherein the two memory control circuits are connected to separate access signal lines, read/write signal lines, and data signal lines, respectively. Data storage device as described.