JPH0262591A - Display data storage device - Google Patents

Abstract

PURPOSE:To decrease the number of components and to reduce the size and cost by storing basic data for display and modification data in the same recording element. CONSTITUTION:A base address(AD) containing an address (AD) signal 3a for discriminating a basic data area and a modification area is inputted from a host computer 1 to a data storage part 17 through a bus 3, an AD selector 14, an AD bus 11, basic data is inputted through the bus 4, a buffer 15, and a bus 20, and a write control signal is inputted through a bus 2, a control selector 18, and a bus 12, so that they are written in specific ADs. When display data is modified, modification data is written by modification address assignment in another host period. The base address containing an AD switching signal 6b is inputted to a storage part 17 through an AD bus 17, a selector 14, and the bus 11, a read control signal is inputted to the storage part 17 through a bus 6 and the selector 18, and the basic data is read out onto the bus 20. The modification AD is inputted through 7, 14, and 17, the modification data is read out of the storage part 17, and the data in the storage part 17 is displayed 19.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to electronic equipment having a data display function.

Conventional technology In recent years, electronic equipment has become more functional and complex, and CRT and L
It has become common to have a screen display function such as a CD, and to display basic data such as characters and supplementary decorative data such as inversion and underlining.

A conventional display data storage device will be described below with reference to the drawings.

FIG. 2 shows an example of a conventional display data storage device.

In FIG. 2, a host controller 2 controls reading and writing of 1-digit display data to the storage section, and 2 is a host system control bus given from 1, which includes data read and write signals and a buffer control signal 2&.

3 is also a host system address bus, 4 is also a host system data bus, 6 is a display controller that controls the display system,
Reference numeral 6 denotes a display system control signal given by 6, which includes a read signal during display operation and a control switching signal 6a. 7 is a display system address bus given by 6, 8 is a modified data bus, 9 is a basic data bus, and 10 is a data converter 1 given by 9.
6, 11a is an address bus for basic data selected by address selector 14, 11b is an address bus for modified data, and 12
selected by the control selector 18, and the data storage section 1T
control signals such as read and write signals given to 13 is an address decoder that generates an element select signal for the storage section from 3, 14 is an address selector, and 14a is 3
Basic address selector that selects and 7 and obtains 11a, 1
4b is a qualified address selector that similarly obtains 11b from 3 and 7. 16 is a bidirectional data buffer between 1 and the storage section, 16a is a basic data buffer, and 16b is a modified data buffer. 17a is a basic data storage element, 17
b is a modification data storage element, each address configuration of which corresponds to an actual display area. Reference numeral 19 denotes a display unit that receives and displays display data from 6.

Regarding the display data storage device configured as above,
The operation will be explained below.

FIG. 3 shows the timing of each signal in this conventional example.

Write and read each data to 17&, 17b6
The switching signal a is divided into a period from the host controller and a period from the display controller, and the address signal and control signal are switched respectively. First, in synchronization with the host period, from the host controller, the basic address including the element select signal is 3 → 14a → 11a1, the basic data is 4 → 16a-'9, and the write control signal is 2 → 1B.
-12 is given, and basic data is written to the specific address 17a. Furthermore, when applying decorations such as underlining or inversion, the modified address is 3 in the same way in another host period.
→14b→11b1 Modification data 4→15b-s, write control signal 2-18-12 is given, and modification data is written to the address corresponding to the basic data of 17b. Note that both data can be read to the host side via 15 using a read control signal at the same control timing as described above.

On the other hand, according to the display scan from the display controller in synchronization with the display period, the display addresses 7→14a→11a1 and 7
→14b-11b, read control signal is 6 → 18 → 12
and is simultaneously given to 17a and 17b. The basic data l'i16 thus read out is converted into double data representing the display format, and is taken into the display controller via 1o and the modification data via 8, interwoven with the display timing signal, and sent to 19. will be displayed. The display controller repeats the above operation while sequentially scanning the addresses, and displays data 19 in 17.

In this way, both controllers can access the display data storage elements at any time in a time-sharing manner.

Problems to be Solved by the Invention However, in the above configuration, two storage elements are required for basic data and modified data, and two sets of address selectors and data buffers are also required. However, there were problems in that it required a large number of parts and was expensive.

The present invention focuses on the above-mentioned conventional technology, and provides a small, low-cost display data storage device with a small number of parts.

Means for Solving the Problems In order to achieve this object, the display data storage device of the present invention is comprised of an address selector, a control signal selector, an address changer, a storage element, and a data latch circuit. has been done.

Operation With this configuration, the host controller and display controller share an address selector and a control signal selector, and also use a latch circuit for display readout, so that both basic display data and modification data can be stored in a single memory. It can be handled with elements.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a display data storage device in one embodiment of the present invention.

In FIG. 1, 1 is a host controller; S2 is a host system control bus containing buffer control signals 2a; 3 is also a host system address bus; 3a is an address signal that distinguishes between a basic data area and a modified data area; is the host data bus. 6 is a display controller that controls the display system; 6 is a display system control signal including a control switching signal 6a; from 6a, a timing generator 21 generates an address switching signal 6b; 7 is a display address bus, 9
is the basic data path, 10 is 9, data conversion unit 16
The display dot signal generated by 11 is the address bus selected by the address selector 14, and 31!1
or switching address signal 11C selected from ψb
including. 12 is a control signal selected by the control selector 18 and given to the data storage section 17; 16 is a control signal selected by the control selector 18 and given to the data storage section 17;
20 is a data bus between 16 and 17, 22 is a latch circuit that holds the read basic data, and 19 is a display section.

Regarding the display data storage device configured as above,
The operation will be explained below.

FIG. 4 shows the timing of each signal of this device. Similar to the conventional example, access to the data storage section is divided into a period from the host controller and a period from the display controller by the control switching signal 6a, and the address signal and the control signal are switched respectively. First, 3a, which became the basic address specification from the host controller in synchronization with the host period.
The basic address including 3-14-11 (11c), the basic data 4-15-20. Write control signal is 2-1
8→12, and basic data is written to the specific address 17. When further modifying the display data,
Another host period, this time with 3a as qualified addressing,
Modification data is written to the corresponding address within the same storage element using the same procedure. Note that both data can be read out to the host side via the readout control signal 16 at the same control timing as described above.

On the other hand, in synchronization with the display period, the display controller gives a basic address of 7 (6b)-14-11 (11C) including 6b, which is designated as a basic address, and a readout control signal of 6-18-12 according to display scanning. From 17, basic data is first read onto 20. Next, 6b switches to modified addressing, and at this time the basic data is latched at 22, converted to dot data representing the display form by 16 via 9, and given to 6 via 10.

Furthermore, the qualified address is 7(6b)-14→11(11
C), the modification data is read from 1T, and 2
It is given to 6 through 0.

The display controller takes in these, interweaves them with a display timing signal, and sends them to 19. The display controller repeats the above operation while sequentially scanning the addresses, and the data in 17 is displayed in 19.

As described above, according to this embodiment, by storing basic display data and modification data in the same memory element, the number of memory elements, various selectors, and buffers required for accessing them can be halved. can.

Note that although the bidirectional data buffer is not essential to the present invention, it is generally used in many cases to improve the reliability of control.

Effects of the Invention As described above, the present invention can reduce the size and cost of the device by storing basic display data and modification data in the same memory element and greatly reducing the number of parts including its peripheral circuits. It can be made cheaper and has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display data storage device in an embodiment of the present invention, FIG. 4 is a signal timing diagram in the same embodiment, and FIG. 2 is a block diagram of a conventional display data storage device. FIG. 3 is a signal timing diagram in the conventional example. 1... Host controller, 6... Display controller, 14... Address selector, 15
・・Bidirectional data buffer, 16 ・・Data converter, 17 ・・Data storage unit, 1B ・・
... Control selector, 19... Display section, 21.
...Timing generator, 22...Latch circuit. Name of agent: Patent attorney Shigetaka Awano and 1 other person

Claims (1)

[Claims] One address selector connected to each of the two control systems, a control signal selector, an address changer that switches part of the address signal, and this address switching stores basic display data and its modification data in the same element. A display data storage device comprising a single storage element and a latch circuit that fixes the basic data read immediately before an address change.