JPS61184587A - Image display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display control device that writes default data into a frame memory of a specific screen to perform default display when multi-screen display is specified.

[Conventional technology]

A conventional device of this type is shown in FIG. In the figure, reference numeral 1 denotes a data bus 11.1 for transmitting image data and address signals, respectively. A central processing unit (hereinafter referred to as CPU) which outputs an address signal to the address bus 12 and accesses the frame memory 4, 2 outputs an address signal to the address bus 1 so as to access all addresses of the frame memory in one frame scanning time.
3 is a CRT controller serving as a display controller that outputs to address bus 1.
Switcher that outputs to 4, 4 is frame memory, 5 is CPU
The period during which I accesses the frame memory 4 (hereinafter referred to as CPU
This is a gate circuit that outputs data from the CPUI to the data bus 15 during the CPU period in a time-division system between a period (hereinafter referred to as a CRT display period) and a period for reading data from the frame memory 4 (hereinafter referred to as a CRT display period).

Next, the operation will be explained. When a drawing command is received from the information sending side when multi-screen display is specified, the CPU sends address signals 3 and image data to the frame memory 4 through address buses 12 and 12, respectively. Output to data bus 11. Here, the switch 3 and the gate circuit 5 are controlled by a signal 16 indicating the time division of the CPU period/CRT display period so that data is written into the frame memory 4 only during the CPU period. Similarly, regarding the default display of a specific screen, when receiving a command from the information sending side to display a certain screen as a default, the CPUI writes the default data stored in the program to all addresses of the corresponding screen during the CPU period. During the CRT display period, the signal 16 is switched to the address signal of the CRT controller 2 by the switch 3, and the frame memory 4 is switched to the address signal of the CRT controller 2.
It only reads data from the .

[Problem that the invention seeks to solve]

However, in the conventional device with the above configuration, default data is written to the frame memory 4 using CPU10 frame memory access like normal image data, which places a burden on the CPU itself and takes time to display the screen. There was a problem.

This invention was made to solve the problems of the conventional technology as described above.
It is an object of the present invention to provide a device that can perform default display of a specific screen at high speed by writing to a frame memory at an access speed using a T controller.

[Means for solving problems]

The image display control device according to the present invention is provided with a storage means for storing default data outputted from the central processing unit, and based on an address signal outputted from the display controller during a period when the display controller accesses the frame memory, The apparatus is provided with timing generating means for generating timing for reading default data from the storage means and writing it into the frame memory when the address signal corresponds to the default data display area.

[Effect]

In this invention, default data from the central processing unit is first stored in the storage means. The default data stored in this storage means is read out during the frame memory access period of the display controller corresponding to the default data display area by the address signal output from the display controller, and written to the address of the frame memory indicated by the address signal. .

〔Example〕

The present invention will be explained below based on the embodiments shown in FIGS. 1 to 3. FIG. 1 is a block diagram showing the configuration of an embodiment, and the same or equivalent parts as in the conventional example shown in FIG. In the figure, 6 is the CPU
1 is a latch circuit serving as a storage means for latching and storing the default data from 1; 7 is a switch for switching between the image data from the CPUI and the default data from the latch circuit 6 and outputting the same to the data bus 15; 8 is a switch When the address of the screen that should be displayed as a default is output from the CRT controller 2 under the control of the signal 17 that specifies the screen that should be displayed as a default from the CPU, a signal that indicates the period for writing default data into the frame memory 4 is generated. An address decoder 9 outputs an address decoder 18, which controls a write signal 19 from the CPUI to the frame memory 4 and a default data write signal 20 from the CRT controller 2 by a signal 18 indicating a period for writing default data, and outputs a write signal 21. This is a gate circuit that outputs to the frame memory 4. In this embodiment, the address decoder 8 and gate circuit 9 constitute timing generating means.

Next, the operation will be explained. Here, as in the conventional example, C
Time division is performed between the PU period and the CRT display period. First, writing data into the frame memory 4 during still image display will be explained.

Upon receiving a drawing command from the information sending side, the CPUI processes the command 1 and sends an address signal and data to the frame memory 4 through the address bus 12. Output to data bus 11. Then, in order to write data to the frame memory 4 only during the CPU period, the switchers 3 and 7 are switched under the control of the signal 16 indicating the time division of the CPU period/CR7 display period, and address signals are sent to the address bus 14 and the data bus 15, respectively. , output the data. The write signal 19 from the CPU 1 passes through the gate circuit 9 and becomes the write signal 2 to the frame memory 4.
1, thereby writing the data into the frame memory 4.

Next, writing of default data to the frame memory 4 in default screen display will be explained. For example, C
FIG. 3 shows a timing diagram in which the RT screen is divided into five as shown in FIG. 2 and only the third screen is displayed by default. The correspondence between the addresses on the frame memory 4 and the screen is shown in FIG. When the CPUI recognizes an instruction from the information sending side to display a specified screen by default, the default data stored in the program is output to the latch circuit 6 and held therein. At the same time, a signal 17 specifying the screen to be displayed as a default is given to the address decoder 8. CR
When the T controller 2 outputs an address signal for a specified screen to the address bus 13, the address decoder 8 outputs a signal 18 as shown in FIG. do. By controlling this signal 18, the gate circuit 9 outputs the default data write signal 20 (
FIG. 3(C)) shows the write signal 21 to the frame memory 4.
3(f)), and the default data read from the latch circuit 6 (FIG. 3(d)) is output from the switch 7 and written into the frame memory 4.

The switch 7 and the CRT controller 2 are controlled by the time division signal 16 (FIG. 3(a)) so that these operations are performed during the CRT display period. Originally, the CRT display period is a period for reading data from the frame memory 4, but when writing default data, writing and reading from the frame memory 4 are performed simultaneously. When the address signal on the address bus 14 (FIG. 3(b)) no longer corresponds to the designated screen, the signal 18 is no longer output. Writing of default data for one frame during the CRT period is performed, and only data reading from the original frame memory 4 is performed during the CRT display period after writing.

In the above embodiment, the address decoder 8 decodes only the frame memory address of a specific screen among the plurality of display areas, but the CPLI 1 can be set to decode the frame memory address of any area of the display screen. In that case, single data can be written and displayed at high speed in any display area.

〔Effect of the invention〕

As explained above, according to the present invention, a storage means is provided for storing default data output from the central processing unit, and the default data is stored based on the address signal output from the display controller during the period when the display controller accesses the frame memory. , by providing timing generation means for generating timing for reading default data from the storage means and writing it into the frame memory when this address signal corresponds to the default data display area, the access speed of the frame memory by the display controller can be increased. Since default data can be written, there is an effect that an image display control device that can perform default display of a specific screen at high speed can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an image display control device according to the present invention, and FIG. 2 is a CR when specifying multi-screen display.
FIG. 3 is a timing chart showing a default display in the above embodiment, and FIG. 4 is a block diagram showing a conventional example. 1... Central processing unit, 2... Jt Is controller, 4... Frame memory, 6... Storage means, 8.
9... Timing generation means. Note that the same reference numerals are used for the middle part of the figure or corresponding parts. Agent Masuo Oiwa (and 2 others) Figure 2

Claims (1)

[Claims] comprising a central processing unit that outputs image data and an address signal to a frame memory and writes the image data; and a display controller that outputs an address signal to the frame memory, reads image data from the frame memory, and displays it on a display; In an image display control device that controls access to the frame memory in a time-division manner, and updates only a specific display area to the default display when specifying a multi-screen display that divides the screen of the display unit into multiple display areas, A storage means is provided for storing default data output from the processing device, and based on an address signal output from the display controller during a period when the display controller accesses the frame memory, this address signal corresponds to the default data display area. An image display control device comprising: timing generation means for generating a timing for reading default data from the storage means and writing it into the frame memory when the default data is read from the storage means and written to the frame memory.