KR950013261A

KR950013261A - Video decoding device

Info

Publication number: KR950013261A
Application number: KR1019930022607A
Authority: KR
Inventors: 권오상; 윤상호
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1993-10-28
Filing date: 1993-10-28
Publication date: 1995-05-17
Also published as: KR970008413B1

Abstract

본 발명은 하나의프레임 메모리와, 프레임 메모리로부터 독출되는 데이타를 기입하고, 기록된 데이타를 움직임보사용 또는 디스플레이용으로 출력하기 위한 버퍼 메모리를구비하여 버퍼 메모리의 동작을 소정의 옵셋을 두어 처리하기 위한 영상복호장치에 관한 것이다. 이를 위하여, 이전 움직임 보상된 데이타와 전송된 차분신호를 더하여 현재 프레임의 데이타를 구하기 위한 신호처리부와, 제1 어드레스버스에 실린 제1어드레스신호에 의해 상기 신호처리부에서 출력되는 데이타를 기록하거나 기록되어 있는 데이타를 독출하기 위한 프레임 메모리와, 상기 신호처리부에서 출력되는 데이타를 제1제어신호에 의해 상기 프레임 메모리로 전송하기 위한 제1삼상태 버퍼와, 제2어드레서 버스에 실린 제2어드레스신호에 상기 프레임 메모리에서 독출되는 데이타를 일시적으로 기록하며 움직임 보상을 위한 데이타는 상기 신호 처리부로 출력하기 위한 버퍼 메모리와, 상기 프레임 메모리에서 독출되는 데이타를 제2제어신호에 따라서 상기 버퍼 메모리로 전송하기 위한 제2삼상태 버퍼와, 상기 프레임 메모리의 기입, 독출 어드레스인 제1어드레스신호, 상기 버퍼 메모리의 기입, 독출어드레스인 제2어드레스신호, 상기 제1및 제2삼상태 버퍼를 제어하기 위한 제1 및 제2제어신호를 생성하기 위한 어드레스생성부와, 디스플레이를 위해 상기 버퍼 메모리에서 독출되는 데이타를 화면에 디스플레이시킬수 있도록 신호 처리하기 위한 디스플레이부로 구성됨으로써, 영상복호 장치를 보다 간단하게 구현한 것이다.The present invention provides a frame memory and a buffer memory for writing data read out from the frame memory and outputting the recorded data for motion assist or display, so as to process the buffer memory at a predetermined offset. It relates to a video decoding device for. To this end, a signal processor for obtaining the data of the current frame by adding the previous motion compensated data and the transmitted difference signal, and recording or recording the data output from the signal processor by the first address signal on the first address bus A frame memory for reading data, a first tri-state buffer for transferring data output from the signal processor to the frame memory by a first control signal, and a second address signal loaded on a second address bus. Temporarily writes data read from the frame memory and transmits data for motion compensation to the signal processor, and transfers the data read from the frame memory to the buffer memory according to a second control signal. Writing and reading a second tri-state buffer and the frame memory An address generator for generating a first address signal that is a dress, a write of the buffer memory, a second address signal that is a read address, and first and second control signals for controlling the first and second tri-state buffers; The display unit is configured to process a signal to display data read from the buffer memory on a screen for display, thereby simplifying an image decoding apparatus.

Description

Video decoding device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 영상보호장치를 나타낸 블럭도,1 is a block diagram showing a conventional image protection device;

제2도는 본 발명에 의한 영상복호장치의 일실시예를 나타낸 블럭도,2 is a block diagram showing an embodiment of an image decoding apparatus according to the present invention;

제3도는 제2도에 도시된 버퍼 메모리를 도시한 상세구조도,FIG. 3 is a detailed structural diagram showing the buffer memory shown in FIG.

제4A 내지 4I도는 제2도에 영상복호장치의 각부의 동작 타이밍도,4A to 4I are operation timing diagrams of the respective parts of the image decoding apparatus in FIG.

제5A, 내지 5F도는 제2도에 영상복호장치의 어드레스버스, 데이타버스 및 제어신호의 타이밍도,5A through 5F are timing diagrams of an address bus, a data bus, and a control signal of an image decoding apparatus in FIG.

제6도는 본 발명에 의한 영상복호장치의 다른 실시예를 설명하기 위한 도면.6 is a diagram for explaining another embodiment of an image decoding apparatus according to the present invention.

Claims

Signal processing means for obtaining data of a current frame by adding previous motion compensated data and transmitted difference signals; Frame recording means for recording the data output from the signal processing means or reading the recorded data by the first address signal loaded on the first address bus; First tri-state buffer means for transferring data output from the signal processing means to the frame memory by a first control signal; Buffer recording means for temporarily recording data read out from the frame recording means by a second address signal loaded on a second address bus, and outputting data for motion compensation to the signal processor; Second tri-state buffer means for transferring data read out from said frame storage means to said buffer recording means by a second control signal; First and second control for controlling the writing of the frame storage means, the first address signal as the read address, the writing of the buffer memory means, the second address signal as the read address, and the first and second three-state buffer means. Address generating means for generating a signal; And display means for signal processing so that data read out from the buffer recording means can be displayed on the screen for display.

An image decoding apparatus according to claim 1, wherein said frame recording means has a capacity corresponding to one frame.

The image decoding apparatus according to claim 1, wherein the first tri-state buffer conducts only during a period in which recording data is loaded on the frame recording means on the first data bus input and output to the frame recording means.

4. The data processing apparatus as claimed in claim 3, wherein the first data bus includes data read from the frame recording means for performing an MC write operation to the buffer memory, and data to be processed by the signal processing means and written to the frame recording means. Image decoding device characterized in that the alternately loaded.

The image decoding apparatus according to claim 1, wherein the first tri-state buffer means conducts only during a period in which frame recording means read data is loaded on a second data bus input / output to the buffer recording means.

The data read from the frame writing means for performing an MC write operation to the buffer memory, and data read from the buffer writing means for MC processing in the signal processing means. And the data read out from the buffer recording means are alternately loaded in time for display.

The image decoding apparatus as claimed in claim 1, wherein the buffer recording means operates by a predetermined offset apart from each other in a write operation for MC processing, a read operation for display, and a read operation for MC processing. .

※ Note: The disclosure is based on the initial application.