KR970008413B1 - Image decoder - Google Patents

Abstract

An image decoding device has a single frame memory and a buffer memory to process the buffer memory's operation with a given offset. This image decoding device includes a signal processing part finding data of the current frame by adding previous motion-compensated data and transmitted differential signal; a frame memory writing data output from the signal processing part by a first address signal carried in a first address bus; a first 3-state buffer for transmitting data output from the signal processing part to the frame memory by a first control signal; a buffer memory temporarily writing data out of the frame memory by a second address signal carried in a second address bus, and producing data for motion compensation to the signal processing part; a second 3-state buffer for transmitting data out of the frame memory to the buffer memory by a second control signal; an address generating part for generating the first and second address signals and the first and second control signals; and a display.

Description

Video decoding device

1 is a block diagram showing a conventional video decoding apparatus.

2 is a block diagram showing an embodiment of a conventional image decoding apparatus according to the present invention.

3 is a detailed structural diagram showing the buffer memory shown in FIG.

4A to 4I are operation timing diagrams of respective parts of the image decoding device shown in FIG.

5A to 5F are timing diagrams of an address bus, a data bus and a control signal of the video decoding apparatus shown in FIG.

6 is a diagram for explaining another embodiment of an image decoding apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

10: signal processing unit 20, 40: three-state buffer (3-State Buffer)

30: frame memory 50: buffer memory

60: address generator 43: display unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus, and more particularly, to a buffer memory including a frame memory and a buffer memory for recording data read from a frame memory and outputting the recorded data for motion compensation or display. The present invention relates to a video decoding apparatus for processing a predetermined offset.

Recently, with the development of computer and digital communication technologies, the demand for digitalizing, storing, and transmitting image information is rapidly increasing. Digital video data is easier to store than analog format, is resistant to noise caused by the surrounding environment, and has various advantages. However, when digitalizing a video signal, a large amount of data is generated. For example, when digitalizing NTSC TV signals, data of 114 Mbps (mega bit per sec) is generated. In addition, it takes about 44 minutes to transmit a single color image at 2400bps with a resolution of 512x512 and 8-bit color components of R, G, and B. Therefore, there has been a demand for image data compression technology for efficiently storing and transmitting the data.

Such compression encoding schemes of image data can be largely classified into a video encoding scheme and a still image encoding scheme according to the configuration. Among them, video encoding may obtain a compression effect by removing redundancy between successive pictures in interframe video.

As an international trend of video data compression technology, Discrete Cosine Transform (DCT), Sub-band Coding, Variable Length Coding (SVC) using spatial correlation. VLC) method, and a method using temporal correlation is a differential coding method using motion compensation, which is applied by Moving Picture Experts Group (MPEG) and ADTV.

FIG. 1 shows a preceding video decoding apparatus, in which two first frame memories 3 record data of a previous frame to be retained for motion compensation, and a second frame memory 4 shows motion compensation. This is to record the data of the current frame obtained by adding the data of the previous frame and the transmitted difference data. The roles of the first and second frame memories 3 and 4 are alternately used depending on the frame type. In order to perform these roles alternately, a multiplexer (MUX) 5 and a demultiplexer (DEMUX) 2 are used as shown.

As described above, two frames are used to store data corresponding to two frames, one frame for each frame. This is due to motion compensation. Since it may be used for motion compensation, the processed data cannot be written at the same position as the position read out from the frame memory.

In addition, the processed data is not only recorded in the frame memory for use in motion compensation of the next frame, but also transmitted to the display unit 8 for display, where the processing unit in the signal processing unit 1 is a reference for motion compensation. Since the unit is a macro block (MB) and the display unit is a line, a slice buffer 7 is provided to convert the macro block unit into a line unit. Therefore, the practical use of a simpler image decoding device having one frame memory has been required.

Accordingly, an object of the present invention is to provide a buffer memory having one frame memory and a buffer memory for writing data read out from the frame memory and outputting the recorded data for motion compensation or display in order to meet the above-mentioned demands. The present invention provides an image decoding apparatus for processing the operation with a predetermined offset.

According to an aspect of the present invention, there is provided a video decoding apparatus comprising: a signal processing unit for obtaining data of a current frame by adding a previous motion compensated data and a transmitted difference signal; A frame memory for writing data to be output from the signal processor or reading data written by the first address signal included in a first address bus; A first tri-state buffer for transmitting data output from the signal processor to the frame memory by a first control signal; A buffer memory for temporarily writing data read out from the frame memory by a second address signal loaded on a second address signal on a second address bus and outputting data for motion compensation to the signal processor; A second tri-state buffer for transmitting data read from the frame memory to the buffer memory by a second control signal; To generate the first and second control signals for controlling the write of the frame memory, the first address signal as the read address, the write of the buffer memory, the second address signal as the read address, and the first, second and three phase buffers. Address generator; And a display unit for signal processing to display data read from the buffer memory on a screen for display.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing an embodiment of an image decoding apparatus according to the present invention. In the block diagram shown in FIG. 2, the current frame is obtained by adding the data read out from the buffer memory 50 and the transmitted difference signal. A signal processing unit 10 for obtaining data of the first data, a first tri-state buffer 20 turned on / off by the first control signal CS1 generated by the address generation unit 60, and the address generation unit 60. A frame memory 30 for writing data to or reading data from the signal processing unit 10 by the first address signal generated by the first address signal AB1 and loaded on the first address bus AB1; A second tri-state buffer 40 that is turned on / off by the first control signal CS2 generated by the first control signal CS2, and a second that is generated by the address generator 60 and included in the second address bus AB2. The data read out from the frame memory 30 by the address signal is temporarily The buffer memory 50 for outputting the data for motion compensation to the signal processor 10 and the display data for the display to the display unit 70, the write, read and buffer addresses of the frame memory 30. And an address generator 60 for generating the write and read addresses of 50) and a display unit 70 for signal processing so that data read from the buffer memory 50 can be displayed for display.

3 is a detailed structural diagram of the buffer memory 50 shown in FIG. 4A to 4I are operation timing diagrams of the respective parts shown in FIG. 2, FIG. 4A is a read address FMRA of the frame memory 30, and FIG. 4B is a read data FMRD of the frame memory 30, and FIG. 4C is a write address BMWA of the buffer memory 50, 4D is a read address MC-BMRA of the buffer memory 50 for MC processing, and 4E is input to the signal processor 10 for MC processing. The read data MC-BMRD of the buffer memory 50 and the 4F diagram signal processor 10 are output from the read data MC-BMRD and the 4F diagram of the buffer memory 50 and output to the frame memory. The data FMWD written in 30, the write address FMWA of the frame memory 30, the read address FMDI of the buffer memory 50 for the display 4H, and the display diagram 4I of FIG. The read data DI-BMRD of the buffer memory 50 for each are shown.

5A is a timing diagram of the address, data bus and control signals of the respective parts shown in FIG. 2, FIG. 5A is the first address bus AB1, and FIG. 5B is the first address generator 60 in FIG. The first control signal CS1 applied to the tri-state buffer 20, FIG. 5C shows the first data bus DB1, and 5D shows the first control signal CS1 applied to the second tri-state buffer 40 from the address generator 60. The second control signal CS2, FIG. 5E shows the second address AB2, and FIG. 5F shows the first data bus DB1.

6 is a view for explaining another embodiment of an image decoding apparatus according to the present invention. Next, the serial operation process of the present invention will be described with reference to the accompanying drawings.

First, in FIG. 2, the frame memory 30 has a capacity corresponding to one frame, and records data processed and output by the signal processor 10 or reads data recorded in the frame memory 30. FIG. To the buffer memory 50. The buffer memory 50 temporarily records data read from the frame memory 30, and outputs data for motion compensation to the signal processor 10 and data for display to the display 70. The address generator 60 generates the write, read address of the frame memory 30 and the write, read address of the buffer memory 50. The signal processor 10 adds the data read out from the buffer memory 50 and the transmitted difference signal to recover the data of the current frame and outputs the data to the frame memory 30.

In FIG. 3, the buffer memory 50 is a case where the MC offset is 2 slides and the display offset is 1 slice. When the operation of the buffer memory 50 is performed one slice at a time, it is composed of four slices. MC write operation for temporarily storing data read from frame memory 30 during operation of buffer memory 50, display read operation for reading to display unit 70, motion compensated data by signal processing unit 10 The MC read operation for outputting is simultaneously performed, and each operation area is performed by one slice vertically as in FIG. 3, and each is circulated vertically.

Now, in conjunction with the timing diagrams of FIGS. 4 and 5, first, during the first slice of one frame, the data is written to the frame memory 30 by the write address FMWA (FIG. 4G) of the frame memory 30. FIG. One slice of data (FIG. 4B) is read from the previous frame data FMWD (FIG. 4F) by the frame memory 30 read address FMRA in FIG. 4A, and the buffer memory 50 in FIG. 4C is written. The data is written to the buffer memory 50 by the address BMWA. As the second slice period starts, the data corresponding to the first slice recorded first in the buffer memory 50 (Fig. 4I) is line-by-line by the buffer memory 50 read address (DI-BMRA) for display in Fig. 4H. Is read and transmitted to the display unit 70. At the same time, the data for the second slice (FIG. 4B) is read out from the frame memory 30 by the frame memory 30 read address FMRA in FIG. 4A and written to the buffer memory 50. FIG. During the third slice period, data corresponding to the second slice recorded in the buffer memory 50 is read out line by line and transmitted to the display unit 70. At the same time, data for the third slice is read from the frame memory 30 and written to the buffer memory 50. In addition, the motion compensated data MC-BMRD (FIG. 4E) required for signal processing for the first slice is also read out from the buffer memory 50 for address processing in the address generator 60 (MC-BMRA; As shown in FIG. 4D, corresponding data is read out and transmitted to the signal processor 10. FIG. At this time, the motion compensated data is read from the first or second slice data according to the motion vector. The operation in the fourth slice period is also the same as in the third slice period. That is, the same is true except that the entire processing data is an area in which one further slice is advanced.

Here, an MC write area for temporarily storing data read from the frame memory 30 arrives in the buffer memory 50 at the last slice area of the buffer memory 50. Therefore, in the fifth slice period, the MC is written in the first slice region. When the fifth slice period is reached, all of the first slice region data is used for display reading or writing to the MC. Therefore, the data may be overwritten with new data.

As described above, since the read operation of the buffer memory 50, that is, the write operation for the MC processing, the read operation for the display, and the read operation for the MC processing are operated separately by a predetermined offset in a vertical cycle, all necessary operations can be performed. Can be.

The MC read data read from the burr memory 50 is transferred to the signal processing unit 10 and added to the transmitted difference data to obtain the data of the current frame. The data is written back to the frame memory 30 for use in the next frame processing. do.

As shown in FIG. 5C, two types of data are loaded in the first data base DB1 alternately in time, and the two data are read from the frame memory 30 to perform an MC write operation in the buffer memory 50. The data FMRD and the data FMWD processed by the signal processor 10 and written in the frame memory 30 are referred to. As shown in FIG. 5A, these two data are generated by the address generator 60 and read by the frame memory 30 loaded on the first address AB1, and at the corresponding address positions by the write addresses FMRA and FMWA. It is read from or written to the frame memory 30. As shown in FIG. 5B, the first tri-state buffer 20 conducts only during the period in which the FMWD is loaded on the first data bus by the first control signal CS1 output from the address generator 60.

As shown in FIG. 5F, the second data bus DB2 includes data FMRD read from the frame memory 30 to perform the MC write operation in the buffer memory 50, and the MC processing in the signal processing unit 10. FIG. The data MC-RD read from the buffer memory 50 and the data DI-RD read from the buffer memory 50 for display are alternately loaded in time. As shown in FIG. 5E, these three pieces of data are generated by the address generator 60 and stored in the buffer memory 50 write address BMWA, MC-BMRA, and DI-BMRA loaded on the second address AB2. This is read or written from the buffer memory 50 at the corresponding address position. As shown in FIG. 5D, the second tri-state buffer 40 conducts only during the period in which the FMRD is loaded on the second data bus by the second control signal CS2 output from the address generator 60. FIG. In the above-described embodiment of the present invention, for the sake of clarity and convenience of implementation, the MC offset is described as two slices, but the motion vector is from -16 to 15+, and the basic unit (MB) of the motion processing is In the case of Fig. 6, the MC offset should be at least 1 slice and 2 macroblocks. Therefore, the above operation can be performed even with other offsets.

As described above, in the image decoding apparatus according to the present invention, a buffer memory includes a frame memory and a buffer memory for writing data read out from the frame memory and outputting the recorded data for motion compensation or display. There is an advantage that can simplify the device by processing the operation of a predetermined offset.

Claims (7)

A signal processing unit for obtaining data of the current frame by adding the previous motion compensated data and the transmitted difference signal; A frame memory for writing data to be output from the signal processor or reading the recorded data by a first address signal loaded on a first address bus; A first tri-state buffer for transmitting data output from the signal processor to the frame memory by a first control signal; A buffer memory for temporarily recording data read from the frame memory by a second address signal loaded on a second address bus, and outputting data for motion compensation to the signal processor; A second tri-state buffer for transmitting data read from the frame memory to the buffer memory by a second control signal; An address generator for generating the first and second address signals and the first and second control signals; And display means for processing a signal suitable for displaying on the screen data read from the buffer memory for display. The video decoding apparatus of claim 1, wherein the frame memory has a capacity corresponding to one frame. The video decoding apparatus of claim 1, wherein the first tri-state buffer conducts only during a period in which data to be written to the frame memory is loaded on a first data bus connected to the frame memory. 4. The data processing apparatus as claimed in claim 3, wherein data read from the frame memory and data to be written to the frame memory are alternated in the first data bus in order to perform a motion compensation write operation to the buffer memory. Video decoding apparatus characterized in that loaded. The video decoding apparatus of claim 1, wherein the second tri-state buffer is conducting only during a period in which data read from the frame memory is loaded on a second data bus connected to the buffer memory. 6. The data processing apparatus as claimed in claim 5, wherein the second data bus includes data read from the frame memory for performing a motion compensation write operation in the buffer memory, and data read from the buffer memory for motion compensation processing in the signal processing means. And the data read out from the buffer memory are alternately loaded in time for display. The image decoding method of claim 1, wherein the buffer memory is characterized in that a write operation for a motion compensation process, a read operation for a display, and a read operation for a motion compensation process are operated by a predetermined offset in a vertical cycle. Device.