KR970003791B1 - Memory device for signal process or in moving imagery - Google Patents

Abstract

A memory device of motion picture signal processor which reads data recorded in a memory to record the data in the memory, display or differential-pulse-code-demodulate it on the basis of an address signal from an address generator for generating data reading address, record address and display address, includes the memory having the capacity to enable recording of n+2 slice data when the frame consits of n slices, a read address generator for generating a read address in order to read data, required for display and differential pulse code modulation, from the memory, a record address generator for changing the recording location of the differential-pulse-code-modulated data according to a motion vector and for generating a record address having the difference by a predetermined offset from the read address, a means for allowing the record address and read address to be supplied to the memory alternately, and a controller for controlling addressing of the address generator and supplying a control signal to the memory.

Description

Memory device of video signal processor

1 is a block diagram of a memory device of a video signal processor according to the present invention.

FIG. 2 is a detailed block diagram of the address generator shown in FIG.

FIG. 3 is a detailed block diagram of an offset generator shown in FIG.

4 is a diagram for explaining a process of writing data into a memory according to the present invention;

* Description of the symbols for the main parts of the drawings *

10: memory 11, 14: offset generator

12,15: adder 13: multiplexer

20: address generation unit 22: display address generation unit

24: write address generator 26: read address generator

30: three-phase buffer 40: control means

42: system clock section 44: counter section

46: change unit 48: dispensing unit

241: large compartment counter 242: h-end comparison

243: line counter 244,264: slice counter

244,265: v-termination comparison unit 250: pixel counter

261: MVP counter 262: MB termination comparison unit

263: MHP counter 267,268,269: adder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for compressing and transmitting an image signal. In particular, the present invention relates to an image signal processor capable of reducing the size of a memory by sharing a current frame memory with a memory for storing a previous frame required for motion compensation prediction encoding. It relates to a memory device.

In a device that processes video such as HDTV, videophone, etc., the video signal has a wider bandwidth than the audio signal. Therefore, a large amount of data is generated when trying to process it digitally. However, the available bandwidth for transmitting it is limited, so data must be compressed to transmit it.

In the related art, when a series of video signals are transmitted, an interframe difference encoding method is used, which extracts and transmits a difference by comparing each pixel corresponding to one screen and the next screen. In this case, the receiver makes the current frame by adding the received difference signal to the signal of the previous frame. Therefore, when processing the current frame, it is necessary to have the data of the previous frame to be referred to in memory. In this case, since the data of the current frame is recorded in the same memory location of the previous frame while the data of the current frame is processed, even one frame memory can be used to sufficiently process the data.

Currently, various techniques for effectively compressing data for transmitting digital video signals have been proposed. Compression techniques commonly used include transform coding schemes that reduce intraframe correlation such as discrete cosine changes, and interframe motion compensation predictive protection scheme that reduces temporal correlation between frames by using motion compensation to reduce temporal correlation between frames. .

Here, motion compensation means that the degree of motion of an object is estimated by a predetermined algorithm in the image signal processing, so that the signal of the previous frame (or field) is obtained from the motion vector (that is, the pixels (or blocks of pixels) of the current frame in the motion image signal. Relative to the previous frame in the direction of how much the vector amount of pixels indicating the movement).

The inter-frame motion compensation predictive encoding method is an image compression method that encodes using the above-described motion compensation, and compares a previous frame and a current frame to estimate how far the image of the current frame has moved compared to the image of the previous frame. Motion compensation is performed using the motion vector and the previous frame, and compression encoding is performed on the difference signal obtained by subtracting the motion compensated signal from the signal of the current frame. In the receiver, the previous frame signal and the motion are compensated for by the motion vector, and this is added to the differential signal to decode the current frame signal.

In other words, unlike the differential coding method, which simply subtracts the value of the current frame from the same position of the previous frame, the method detects motion information between the previous frame and the current frame and places the smallest difference in the motion search region. Find the difference with the part.

In this case, as in the differential coding scheme, the transmitter and the receiver each need a memory in which the previous frame is recorded. However, in this case, since the previous frame data of the position to be decoded is used for the motion compensation of the adjacent part, that is, it belongs to the motion search area, and if the decoded data is recorded at the same position of the previous frame, this causes the motion compensation of the adjacent part. You won't be able to.

Therefore, in the related art, this is handled by two frames of memory, the current frame and the previous frame. Thus, using two separate frame memories has a problem of increasing the price of the transmitter and the receiver and occupying a considerable volume in the transmitter and the receiver.

Accordingly, the present invention has been made in view of the above-described problems of the prior art, and a memory device of a video signal processor capable of reducing the amount of frame memory required by a transmitting side and a receiving side in an inter-frame motion compensation predictive encoding scheme. The purpose is to provide.

In order to achieve the above object, the present invention provides a method of writing data into a memory based on an address signal from an address generator which generates a read, write and display address of data or writes data into a memory for display and differential pulse code modulation. A memory device of a moving picture signal processor for reading a memory, comprising: the memory having a capacity to record n + 2 slice data when a frame is composed of n slices, and from this memory to display and differential pulse code modulation; Read address generating means for generating a read address for reading the necessary data, and write address generation for changing a write position of the differential pulse code modulated data according to a motion vector and generating a write address having a predetermined offset difference from the read address. Way And a control means for alternately providing a control signal to the memory in which a write address and a read address are alternately provided.

Further, in the memory device of the present invention having the configuration as described above, the means for alternately providing an address to the memory includes a vertical rotation of the position at which the frame data is written to the memory in units of frames by a write operation. It functions to add a predetermined offset to the address as much as possible.

Further, the control means included in the memory device of the present invention is a counter for providing a multiplexer with a selection signal for providing an address signal from the address generator to the multiplexer and inputting a system clock to the memory and providing a write / read control signal to the memory. And a divider for bit-converting the output signal from the counter and providing the buffer as an enable signal, and a divider for dividing the system clock into four and providing the address generator.

Other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a memory device of a video signal processor according to an exemplary embodiment of the present invention. As shown in the figure, the memory device of the present invention comprises a memory 10 for recording data of a previous frame and data of a current frame from a DPCM circuit output, a display address generator 22, and a read address generation. And an address generator 20 for generating a write address and a read and display address of data to the memory 10, and a differential pulse code not shown in the drawing. Control means 40 for adjusting the addressing of the three-phase buffer 30 and the address generator 20 for data transfer between the modulation circuit and the display unit and providing control signals to the memory 10 and the three-phase buffer 30. ).

In addition, the above-described control means 40 inputs the system clock from the system clock section 42 to provide the multiplexer 13 with a selection signal for providing an address signal from the address generator 20 to the memory. And a counter unit 44 which provides a write / read control signal to the memory 10, and converts a 2-bit output signal from the counter unit 44 into 4 bits to provide the buffer 30 as an enable signal. The changer 46 and the divider 48 divide the system clock into four and provide the address generator 20 to the address generator 20. In the figure, reference numerals 11 and 14 denote offset generators, and 12 and 15 denote adders, respectively.

FIG. 2 shows a detailed block diagram of a display, read and write address generator in the address generator included in the memory device of the present invention shown in FIG. The display address generator 22 in the present invention generates the display address RA0-18 to read the data necessary for display, and the data recorded in the memory is read out one line. In the figure, the pixel counter 250 indicates the horizontal pixel position in the macro compartment as the address R0-3 while counting 16 horizontal pixels in the macro compartment as a system clock divided into four. The giant compartment counter 241 counts 44 giant compartments on one line with a carry of the pixel counter 250 and indicates the positions of the giant compartments as addresses R4-9. The h-end comparison unit 242 determines whether one line is terminated and resets the large compartment counter. The line counter 243 counts the line termination signal from the h-end comparison unit 242 to indicate the positions of 16 lines constituting one slice as addresses R10-13. The slice counter 244 counts the signal carried by the line counter 243 to represent 60 slices constituting one frame by the address R14-18. The V-ending comparison unit 245 determines whether all 60 slices have been counted, and resets the slice counter 244.

Next, the write address generator 24 generates an address necessary for writing the DPCM output data to the memory 10. Accordingly, the data output from the DPCM is recorded in the memory 10 shown in FIG. As shown in FIG. 2, the pixel counter 250 is commonly used with the display address generator 22. The macroblock vertical pixel (MVP) counter 261 represents the address W10-13 while counting 16 pixels vertically in the macroblock as a carry of the pixel counter 250. The MB end comparison unit 262 indicates whether the output of the MVP counter 261 is the end of the large block. A mega block horizontal pixel (MHP) counter 263 counts the end of one macro block to indicate the horizontal pixel position of the macro block by the address W4-9. The slice counter 264 counts carry from the MHP counter 263 to represent 60 slices constituting one frame by the address W14-18. The V-ending comparison unit 265 determines whether all 60 slices have been counted, and resets the slide counter 264.

The write address is generated as described above, and the read address is obtained by adding a motion vector to the write address and adding a predetermined offset.

In the same figure, the adder 267 adds the vertical motion vector MVV to the address W10-13, and the adder 268 adds the horizontal motion vector MVH to the address W0-9. The adder 269 adds an offset address to the output of the adder 267. The offset is just n when a frame consists of n slices. In this embodiment, since n = 60, 60 is an offset value.

Next, an operation process of the memory device of the video signal processor according to the present invention having the configuration as described above will be described.

As shown in FIG. 1, the counter unit 44 in the control means 40 provides the system clock as an input and provides the selection signals S0 and S1 to the multiplexer 13. An example of the selection signal is as follows. As shown in Table 1.

TABLE 1

In addition, S1 of the above-described selection signals is also input to the R / W terminal of the memory 10.

The buffer 30 buffers data input / output to or from the memory 10, and the control signals of the respective buffers are selected from the counter unit 44 by the selection signals S0 and S1. The signal is converted through.

As shown in FIG. 2, the system clock signal generated by the system clock section 42 is divided into four through the divider 48, and this signal is input to the address generator 20. FIG. The four-divided signal generates the address RA0-18 through the display address generator 22. This address is configured to read data in memory one line at a time. On the other hand, when the 2-bit selection signal of the system clock reaches 00, the multiplexer 13 provides a display address to the memory, and at this time, the output of the counter unit 44 which is also input to the R / W terminal of the memory 10 (S1). ) Is 0 so data display and read operations are performed. The read data is output through the buffer 30 to the display circuit and the DPCM input unit not shown in the same drawing.

Next, a write address WA0-18 for writing data input from the DPCM circuit into the memory 10 is generated in the write address generator 26. FIG. At this time, the write address is configured to record in a large block unit. The signal input from the DPCM is written to the memory 10 through the buffer 30 when the selection signal input from the counter 44 to the multiplexer 13 is 01. The read address for reading data to be output to the DPCM input unit is generated by the read address generator 26, is added to a motion vector input to another path, and the write position is changed, and has a difference by an offset from the read address. .

In the operation of the memory device of the present invention as described above, a process of reading the data of the previous frame and writing the data of the current frame to the memory will be described in more detail with reference to FIGS. 3 and 4.

In Fig. 1, offset 1 represents an offset between a read address and a write address, and its value is N. The adder 12 is a modulo N + 2 adder (when the output value of a normal adder is divided by N + 2). The rest as output). Offset 2 is for realizing this since the read slice address is cyclically increased by N than the read slice value of the previous frame, the details of which are as shown in FIG. As can be seen from the figure, the input data of the latch 301 becomes output data to the previous clock, the clock is frame synchronized, and the adder 302 is an N adder as a module as well. .

O, N, N-2 (= N + N mod N + 2), N-4 (= N-2 + N mod N + 2),... …

Therefore, assuming that the search area required for motion compensation of a frame spans vertically neighboring slices, the data of the slice currently processed may be overwritten in the area where data corresponding to the position of the previous frame is recorded. none. This is because data at that position of the frame is used for motion compensation of the next slice. Therefore, the capacity of the memory 10 is a capacity capable of recording 1 frame + 2 slice data, and as shown in FIG. 4, the first processed slice is an area where the slice address is N by using an extra slice area. The second slice is recorded in the region having the slice address N + 1, and the third slice is recorded in the region having the slice address 0 again, thereby recreating the newly recorded data with the region in which the previous frame was recorded. Therefore, if the slice address is offset by N to be recorded, even if the overwrite is performed, the data corresponding to the overwrite position is not used for the next motion compensation, so that the problem as described above is not caused.

As such, the relationship between the read and write slice addresses for the frame is shown in FIG. 4, which is again shown in Table 2 below.

TABLE 2

As described above, according to the present invention, the system is configured such that the read address and the write address are cyclically offset by N in the slice address.

As described above, the memory device of the present invention can simultaneously share the motion compensated data of the previous frame and the current frame in one frame memory. Therefore, due to such a structure, the data of the previous frame to be used as a reference for future motion compensation remains intact in memory, and the position where the motion compensation ends in the current frame and is not used for motion compensation of other parts. Portions of the previous frame are updated with the current frame data that is motion compensated.

Therefore, according to the memory device according to the present invention, it is possible to reduce the amount of memory of the video signal processor while performing the same function, thereby reducing the manufacturing cost of the entire system.

Claims (6)

Memory device of a moving picture signal processor that writes data to a memory based on an address signal from an address generator that reads, writes and displays data and reads the data recorded in the memory for display and differential pulse code modulation. A memory comprising: a memory capable of writing n + 2 slice data when the frame consists of n slices; Read address generating means for generating a read address to read data necessary for display and differential pulse code modulation from the memory; Recording address generating means for changing the recording position of the differential pulse code modulated data according to a motion vector and generating a recording address having a difference by a predetermined offset from the read address; Means for causing the write address and read address to be alternately provided to the memory; And a control means for adjusting addressing of the address generator and providing a control signal to the memory. The memory device of claim 1, wherein the offset is n / 2 + 2 slices. 2. The apparatus of claim 1, wherein the means for alternately providing an address to the memory adds a predetermined offset to the address such that the position at which the frame data is written to the memory in a unit of frame by a write operation is vertically circulated. Memory device of a video signal processor, characterized in that the device. 2. The counter of claim 1, wherein the control means inputs a system clock and provides a multiplexer with a selection signal for providing an address signal from the address generator to the memory and a write / read control signal to the memory. And a divider for bit-converting the output signal from the counter and providing the buffer as an enable signal, and a divider for dividing the system clock into four and providing the address generator. Memory device for video signal processor. 5. The memory device of claim 4, wherein the counter unit is a 2-bit counter. The memory device of claim 4, wherein the converter converts a 2-bit signal from the counter into a 4-bit signal.