KR100248651B1 - A motion compensator - Google Patents

Abstract

In the image decoder, the motion compensation apparatus includes: a motion compensation controller (100) for receiving a motion vector and a flag to generate a motion compensation control signal and adjusting a timing for a calculation process; A memory controller 200 which receives a motion vector and a flag and generates a read / write address signal and a memory control signal; A memory (300) for reading or writing pixel data compensated according to the address signal; A bus controller 400 for outputting a bus control signal; A common bus 500 for transmitting the compensated pixel data; And a motion compensation unit 600 which performs motion compensation using pixel data input from the common bus 500 and inverse discrete cosine transform data according to the motion compensation control signal. According to the present invention, since the video decoder includes a block that performs an interfacing function between blocks having different operating speeds, motion compensation can be efficiently performed using inverse discrete cosine transformed image data and a motion vector. .

Description

Motion compensation device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation device. In particular, motion compensation (MC) is performed by using image data and a motion vector (mv) obtained by an inverse discrete cosine transform (IDCT) in a video decoder. The present invention relates to a motion compensation device configured to efficiently perform motion compensation.

In general, band compression is absolutely necessary for transmission of a high definition television (HDTV) signal. There are three methods for compressing a band. First, a technique for reducing the amount of transmission information by using a relationship between a picture and a next picture, that is, a motion vector (mv), and second, Discrete Cosine Transformation (DCT) and quantization (QT) for compressing information in a picture. Quantization (VT) technique and thirdly, Variable Length Coding (VLC) technique for converting the transformed information into bits of appropriate size by stochastic distribution.

Motion compensation in the band compression technique refers to a technique for reducing the amount of image data by using a motion vector detected during image encoding in order to reconstruct an image with better image quality. In video coding, motion compensated coding is performed to remove temporal redundancy in order to obtain a high data compression rate. Such motion compensation coding methods include MPEG (Moving Picture Expert Group) and H.261 (ITU-T: International). It is also an important part of international video coding standards such as Telecommunication Union-one of the recommended numbers defined in Telecommunication Standardization.

The core technique of the motion compensation coding technique is to detect motion vectors, which are generally divided into a block matching algorithm (hereinafter referred to as BMA) and a pixel recursive algorithm (hereinafter referred to as PRA). Lose. In terms of data reduction, the PRA method is superior to the BMA method, but in terms of system complexity, the BMA method, which is processed in units of blocks, is widely used for most motion coding because it requires less computation and easier hardware implementation than the PRA method, which is processed in units of pixels. have. When estimating motion with BMA, the most common search method is the full search algorithm, which searches for all blocks within the search area of the previous frame and then closes the block most similar to the reference block of the current frame. This is the best way to find.

Techniques related to motion compensation are disclosed in US Pat. Nos. 5,379,076, 5,469,517, 5,473,379, and the like. Such motion compensation coding is performed by performing a motion estimation and compensation using a previous frame and a difference signal between the compensated image and the original image. The encoding process is performed. The more accurate the estimation of the motion is, the simpler the difference signal can be obtained, thereby improving the coding efficiency.

As described above, after a motion encoder obtains a motion vector and transmits the motion vector, the video decoder performs motion compensation using the inverse discrete cosine transformed image data and the motion vector. A need arises.

Accordingly, the present invention has been made to meet the necessity as described above, and provides a motion compensation device that is capable of efficiently performing motion compensation using an inverse discrete cosine transformed image data and a transmitted motion vector in an image decoder. The purpose is.

The motion compensation apparatus according to the present invention for achieving the above object, receives a motion vector and a flag to generate a motion compensation control signal for controlling the motion compensation process, and adjust the timing for the process of calculating the motion compensation A motion compensation control unit;

A memory controller configured to receive a motion vector and a flag and generate a read / write address signal and a memory control signal;

A memory for reading or writing compensated pixel data in accordance with an address signal from the memory controller;

A bus controller which outputs a bus control signal;

A common bus for transmitting the compensated pixel data to be stored in the memory according to a bus control signal from the bus controller; And

And a motion compensation unit configured to perform motion compensation using pixel data inputted from the common bus and inverse discrete cosine transformed data according to the motion compensation control signal from the motion compensation control unit.

1 is a conceptual block diagram of a typical MPEG-2 video decoder;

2 is a block diagram of a motion compensation device according to the present invention.

* Explanation of symbols for main parts of the drawings

100: motion compensation controller 200: memory controller

300: memory 400: bus control unit

500: common bus 600: motion compensation unit

610: input buffer 630: half-pixel compensation unit

650: summer 670: output buffer

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

For better understanding of the present invention, the encoding process, motion vector estimation, and motion compensation prediction according to each picture applied to MPEG-2 will be described below.

The I (Intra) -picture removes only redundancy in the spatial direction by applying a discrete cosine transform (DCT) for each block. Because of the structure of the Group of Pictures (GOP), the quality of an I-picture has a significant impact on the quality of the entire group of pictures (P (Predicted)-an important influence on the encoding performance of pictures). Should be. To this end, intraframe coded images are processed separately from the interframe technique in quantization and Huffman entropy encoding to maintain high quality.

P (Predicted) -picture compresses data using forward interframe predictive coding and discrete cosine transform. The motion compensation type predictive technique is applied to the current input image based on the previous I-picture and P-picture to compensate for the change caused by the motion of the object. Because of the structure of a picture group (GOP), the P-picture affects the picture quality of consecutive P-pictures and Bidirectional predicted (B) pictures within a picture group, so it is less than I-picture but less than B-picture. Allocate many bits and encode them.

Bidirectional predicted (B) -picture compresses data using bidirectionally interframe predictive coding and discrete cosine transform. Three inter-image predictions using the motion-compensated predicted and motion compensated interpolated images from the previous I-picture and the P-picture and the next P-picture, respectively, for the current input image. After the signal is obtained, the best of these prediction signals is selected as the prediction signal between the images to remove the redundancy between the images. After that, the discrete cosine transform and the quantization process are applied to the prediction error from which the redundancy between the images is removed. Because of the structure of the picture group, the quality of the B-picture does not affect other pictures in the picture group. Therefore, encoding is performed by allocating relatively few bits in consideration of subjective picture quality.

Meanwhile, in MPEG-2, methods for motion estimation (ME) and motion compensation (MC) include frame motion compensation (frame MC), field motion compensation (field MC), and dual prime motion compensation (dual prime MC). Basically, all motion estimation and compensation are required to be half pixel unit.

Frame motion estimation and compensation is a motion estimation method that has been used since MPEG-1. This method estimates and compensates motion in a frame structure without distinguishing between upper and lower fields, and applies a macroblock (MB) to encode a current frame. The full search is performed to the half-pixel precision in the search region of the reference frame, and the position generating the smallest mean absolute error (MAE) is determined as the motion vector. Since the data is substantially given in pixel units, the pixel-by-pixel motion vector is obtained through the first-order full search in pixel units, and then the motion vector in half-pixel units is obtained through the inter-pixel interpolation and the second search. In the case of frame motion estimation, P-picture transmits one motion vector per macroblock, and B-picture transmits one or two motion vectors per macroblock, compared to field motion estimation and compensation. The number of bits required for motion vector transmission is small.

In addition, field motion estimation and compensation (field ME / MC) is a method of performing motion estimation and compensation for each field in a picture of a frame structure. After the four motion vectors of the upper, lower, upper, upper, lower, upper, lower, and lower positions are obtained in units of 16 * 8 sub-macroblocks, respectively, between fields, and then the minimum and uppermost fields of the current field One motion vector is selected to generate a motion compensation error. Accordingly, two motion vectors are transmitted per macroblock in a P-picture, and two or four motion vectors are transmitted in one macroblock in a B-picture. On the MPEG-2 video encoder side, all the macroblocks are applied to the frame / field prediction method, and then the prediction mode having the smaller prediction error is used. On the image decoder side, since the prediction mode used by the image encoder is transmitted, motion compensation is performed to restore the image.

Dual prime motion estimation and compensation is then known to be effective for sequences with relatively slow motion by transmitting only one motion vector and differential motion vector (dmv) per macroblock. If the B-picture is allowed, this method can obtain better image quality, but otherwise, the use of dual prime prediction can improve the image quality with as little bit generation as possible. In the dual prime prediction method, the upper, lower, upper, upper, lower, and lower lower motion vectors obtained in the field prediction mode are used as the basic motion vectors as they are. The upper and lower motion vectors are scaled (* 2, * 2/3) and truncated respectively to form a basic motion vector, and then horizontally and vertically with respect to each of the four basic motion vectors. By fine adjustment of -1, 0, and 1, the basic motion vector and displacement value (dmv) are sent to minimize the motion compensation error for two 16 * 8 sub macroblocks. Since dual prime motion estimation requires a large amount of computation in the image encoder, it is necessary to calculate nine prediction candidates per one basic motion vector. Therefore, one of a total of 36 candidate motion vectors and a differential motion vector must be calculated. On the other hand, since the image decoder only needs to calculate two field motion vector values from the transmitted basic motion vector and the differential motion vector value, it is relatively simple to implement.

1 is a conceptual block diagram of a typical MPEG-2 video decoder, in which a video decoder is a buffer 10, a demultiplexing and variable length decoding block 20 (DeMux & VLD), an inverse quantization block 30 IQ, and inverse discrete. The cosine transform block 40 is composed of an IDCT, a motion compensation block 50, and a selection block 60.

As shown in FIG. 1, the buffer 10 receives an encoded bit stream transmitted from an image encoder (not shown), performs buffering, and then outputs the buffered bit stream.

The demultiplexing and variable length decoding block 20 receives the buffered bit stream from the buffer 10 and performs demultiplexing and variable length decoding (VLD) to perform quantization level, discrete cosine transform mode, and motion compensation. Print information. Here, the variable length decoding (VLD) is performed because the variable length coding (VLC) is performed in the image encoder.

The inverse quantization block 30 dequantizes the variable length decoded image data according to the quantization level information input from the demultiplexing and the variable length decoding block 20. Here, the reason for performing inverse quantization (IQ) is because of the image encoder. This is because quantization (Q) is performed at.

The inverse discrete cosine transform block 40 is inverse discrete for inverse quantized image data according to the discrete cosine transform mode information (information on whether a field DCT or a frame DCT) input from the demultiplexing and variable length decoding block 20. The cosine transform is performed. The reason for performing the inverse discrete cosine transform (IDCT) is that the discrete cosine transform (DCT) is performed in the image encoder.

The motion compensation block 50 is inverse discrete cosine transformed from the inverse discrete cosine transform block 40 according to the motion compensation information (ie, the motion vector and the flag) input from the demultiplexing and the variable length decoding block 20. Motion compensation is performed by receiving image data. The present invention relates to the motion compensation block 50.

Finally, the selection block 60 selects and outputs one of the inverse discrete cosine transformed image data from the inverse discrete cosine transform block 40 or the motion compensated image data from the motion compensation block 50.

2 is a block diagram illustrating a motion compensator according to the present invention. The motion compensator according to the present invention includes a motion compensator 100, a memory controller 200, a memory 300, a bus controller 400, and a common bus ( 500 and the motion compensator 600.

The motion compensation control unit 100 receives a motion vector mv and a flag from the variable length decoder (see FIG. 1) to generate a motion compensation control signal for controlling the motion compensation process, and generates a motion compensation signal. Adjust the timing for the calculation process. In this case, a flag is a signal for indicating whether the data is valid data ("decoded _pels"), an I-picture, a P-picture, or a B-picture signal ("picture_coding_type"). "", "Picture_structure" signal indicating whether it corresponds to a higher field, a lower field, or a frame picture, "motion_type" indicating a type of motion, field discrete cosine transform or frame discrete cosine transform. A signal ("dct_type") and a signal ("macroblock_motion_forward" and "macroblock_motion_backward") indicating which prediction corresponds to one of the forward, backward, and bidirectional predictions.

The memory controller 200 receives a motion vector mv and a flag from a variable length decoder (see FIG. 1) to generate a read / write address signal and a memory control signal.

The memory 300 reads or writes the compensated pixel data according to the address signal from the memory controller 200. The memory 300 includes four frames (I-picture, B-picture, P-). Pictures, etc.).

The bus controller 400 outputs a bus control signal.

In the common bus 500, compensated pixel data to be stored in the memory 300 according to a bus control signal from the bus controller 400 and compensated pixel data to be sent to another functional block such as a display unit (not shown). The common bus 500 is configured to transmit 12 pixels (pel), that is, 96 bits of pixel data.

The motion compensator 600 inverts the pixel data input from the common bus 500 and the inverse discrete cosine transforming part (see FIG. 1) 40 according to the motion compensation control signal from the motion compensating control part 100. Motion compensation is performed using discrete cosine transformed data.

Meanwhile, referring to FIG. 2, the motion compensator 600 includes an input buffer 610, a half pixel compensator 630, an adder 650, and an output buffer 670. The reason why the input buffer 610 and the output buffer 670 are provided inside the motion compensator 600 is that the operating speeds of the memory 300 and the motion compensator 600 are different. That is, the memory 300 operates at 81 MHz, and the motion compensator 600 operates at 54 MHz.

In the input buffer 610, 12 from the memory 300 according to the motion compensation control signal (start_block: signal indicating the start of a block, which is used to start counting) from the motion compensation control unit 100. The pixel data in the pixel unit is input through the common bus 500 to be interfaced, and then output in 9 pixel units. In this case, the input buffer 610 may be implemented to process data in block units. The half-pixel compensator 630 generates a signal from the input buffer 610 according to the motion compensation control signal from the motion compensation controller 100, that is, a signal hpctl indicating whether or not to perform half-pixel compensation. Pixel data for the I-picture, P- according to the signal (mb_type) indicating the pixel data in the pixel unit or half-pixel compensation or output as it is in 2 pixel units and indicating which prediction corresponds to forward, reverse or bidirectional prediction. The pixel data of the picture or the average value of the pixel data of the I-picture and the P-picture is output in units of two pixels.

In the adder 650, a motion compensation control signal from the motion compensation controller 100 (dct_type: a signal indicating whether a field DCT is performed or a frame DCT is performed, and mc_type: indicating a type of motion compensation is performed). The pixel data from the half pixel compensation unit 630 and the pixel data of the two pixel units from the inverse discrete cosine conversion unit (refer to FIG. 1) 40 are output according to the signal.

The output buffer 670 outputs the pixel data of the compensated two-pixel unit from the summing unit 650 to the common bus 500 in 12 pixel units for storing in the memory 300 according to a field method. In this case, the output buffer 670 may be implemented to process pixel data in macroblock units.

Next, an operation of an embodiment of the motion compensation apparatus according to the present invention will be described with reference to the accompanying drawings. In particular, referring to FIG. 2, the motion compensation process is described in order according to each picture.

1) When I-picture is input

When the I-picture is inverse discrete cosine transformed by the inverse discrete cosine transform block of the image decoder (see FIG. 1) and input to the adder 650 of the motion compensator 600, the motion compensator 600 is output as it is. It is stored in the buffer 670. For the I-picture, the image encoder (not shown) removes only the redundancy in the spatial direction by applying the discrete cosine transform, so that motion compensation does not need to be performed in the image decoder. Therefore, the motion vector value input to the motion compensation control unit 100 is "0". The I-picture stored in the output buffer 670 of the motion compensator 600 is moved to the common bus 500 by 12 pixels (96 bits) in a field method according to the motion compensation control signal of the motion compensation controller 100. Is output. At this time, the common bus 500 is controlled by the bus controller 400. In addition, the memory controller 200 which receives the motion vector " 0 " and the flag from the variable length decoding block (see FIG. 1) 20 outputs a write address signal and a memory control signal to store the I-picture data. . Then, the memory 300 stores the I-picture data in the common bus 500 in a predetermined memory area according to the write address signal and the memory control signal from the memory controller 200.

2) When P-picture is input

When a motion vector and a flag for a P-picture are input to the motion compensation controller 100 and the memory controller 200 from the variable length decoding block (see FIG. 1) of the image decoder, the motion compensation controller 100 moves. Various control signals (start_block, hpctl, mb_type, dct_type, mc_type, out_buffer_start) necessary for compensation are generated, and the memory controller 200 outputs a read address signal and a memory control signal according to a motion vector and a flag to refer to the motion compensation. The pixel data of the I-picture to be read is controlled from the memory 300. The pixel data of the I-picture read from the memory 300 is input to the input buffer 610 of the motion compensator 600 by 12 pixels through the common bus 500, wherein the common bus 500 is a bus controller. The input buffer 610 receives a signal (“start_block”) indicating the start of a block from the motion compensation controller 100 and stores data in units of blocks, and then controls the pixel by 9 pixels. Output the data. When pixel data of an I-picture output by nine pixels is input to the half-pixel compensator 630, half-pixel compensation is performed according to a performance signal “hpctl” for half-pixel compensation from the motion compensation controller 100. After this, two pixels are output. The I-picture pixel data of the two pixel unit and the inverse discrete cosine-converted P-picture pixel data of the inverse discrete cosine transform block (refer to FIG. 1) from the half-pixel compensator 630 When input to the adder 650, the two data are combined according to the motion compensation control signals dct_type and mc_type of the motion compensation control unit 100, and then output in units of 2 pixels after the compensation is performed. Do not become negative. When the compensated pixel data for the P-picture from the summing unit 650 is input to the output buffer 670, 12 pixels are common buses by 12 pixels according to the motion compensation control signals dct_type and out_buffer_start of the motion compensation controller 100. Is output to 500. The compensated pixel data for the P-picture output to the common bus 500 is stored in a predetermined area of the memory 300 by a write address signal and a memory control signal from the memory controller 200.

3) When B-picture is input

When a motion vector and a flag for a B-picture are input to the motion compensation controller 100 and the memory controller 200 from the variable length decoding block (see FIG. 1) of the image decoder, the motion compensation controller 100 moves. Various control signals (start_block, hpctl, mb_type, dct_type, mc_type, out_buffer_start) necessary for compensation are generated, and the memory controller 200 outputs a read address signal and a memory control signal for forward motion compensation according to a motion vector and a flag. The pixel data of the I-picture to be referred to is controlled to be read from the memory 300. The pixel data of the I-picture read from the memory 300 is input to the input buffer 610 of the motion compensator 600 by 12 pixels through the common bus 500, wherein the common bus 500 is a bus controller. The input buffer 610 receives a signal (“start_block”) indicating the start of a block from the motion compensation controller 100 and stores data in units of blocks, and then controls the pixel by 9 pixels. Output the data. When pixel data of an I-picture output by nine pixels is input to the half-pixel compensator 630, half-pixel compensation is performed according to a performance signal “hpctl” for half-pixel compensation from the motion compensation controller 100. After this is done, it is stored for a while. In addition, the memory controller 200 controls to read the pixel data of the P-picture to be referred to from the memory 300 by outputting a read address signal and a memory control signal for backward motion compensation according to the motion vector and the flag. The pixel data of the P-picture read from the memory 300 is input to the input buffer 610 of the motion compensation unit 600 by 12 pixels through the common bus 500, wherein the common bus 500 is a bus controller. The input buffer 610 receives a signal (“start_block”) indicating the start of a block from the motion compensation controller 100 and stores data in units of blocks, and then controls the pixel by 9 pixels. Output the data. When the pixel data of the P-picture output by nine pixels is input to the half-pixel compensator 630, half-pixel compensation is performed according to a performance signal “hpctl” for half-pixel compensation from the motion compensation controller 100. After this is done, it is stored for a while. The half-pixel compensator 630 also stores an average value of pixel data of the I-picture and the P-picture for bidirectional motion compensation. In this case, the pixel data of the I-picture, P which is temporarily stored in the half-pixel compensation unit 630 according to information (mc_type) of which forward, reverse, or bidirectional motion compensation from the motion compensation control unit 100 is selected, P One of the average values of the pixel data of the picture and the pixel data of the I-picture and the P-picture is selected and output in units of two pixels. The pixel data in two pixel units selected and output from the half pixel compensator 630 and the B-picture pixel data in inverse discrete cosine transformed in two pixel units from an inverse discrete cosine transform block (see FIG. 1) are summed. When input to the unit 650, the two data are summed according to the motion compensation control signals dct_type and mc_type of the motion compensation control unit 100, and then output in units of 2 pixels after compensation. Don't be negative. When the compensated pixel data for the B-picture from the summing unit 650 is input to the output buffer 670, the common bus is provided for 12 pixels in accordance with the motion compensation control signals dct_type and out_buffer_start of the motion compensation controller 100. Is output to 500. The compensated pixel data for the B-picture output to the common bus 500 is stored in a predetermined area of the memory 300 by a write address signal and a memory control signal from the memory controller 200.

As described above, motion is compensated and the pixel data stored in the memory 300 are transmitted to a display block (not shown) through the common bus 500 under the control of the bus controller 400 to be displayed. .

On the other hand, the reference numerals written in the components of the claims of the present application to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

In addition, the above-described embodiments are merely illustrative in all respects and should not be construed limitedly, and all modifications existing within the true spirit and scope of the present invention shall fall within the claims of the present invention.

As described above, according to the present invention, when performing the motion compensation in the image decoder, the operation speed of the memory 300 storing the motion compensated pixel data and the motion compensation unit 600 which actually performs the motion compensation are properly adjusted. By providing a block for interfacing inside the motion compensation block, the motion compensation can be performed smoothly.

Claims (3)

A motion compensation control unit 100 for receiving a motion vector and a flag, generating a motion compensation control signal for controlling a motion compensation process, and adjusting a timing of a motion compensation calculation process; A memory controller 200 which receives a motion vector and a flag and generates a read / write address signal and a memory control signal; A memory 300 that reads or writes compensated pixel data according to an address signal from the memory controller 200; A bus controller 400 for outputting a bus control signal; A common bus 500 for transmitting the compensated pixel data to be stored in the memory 300 according to a bus control signal from the bus controller 400; And And a motion compensation unit 600 performing motion compensation using pixel data input from the common bus 500 and inverse discrete cosine transformed data according to the motion compensation control signal from the motion compensation control unit 100. In response to the motion compensation control signal from the motion compensation controller 100, the motion compensator 600 receives the pixel data from the memory 300 through the common bus 500 to perform interfacing. An input buffer 610 which is outputted afterwards; A half-pixel compensation unit 630 for performing half-pixel compensation or outputting pixel data input from the input buffer 610 according to the motion compensation control signal from the motion compensation control unit 100; An adder 650 for summing and outputting pixel data from the half-pixel compensator 630 and inverse discrete cosine transformed pixel data according to a motion compensation control signal from the motion compensation controller 100; And an output buffer (670) outputting the compensated pixel data from the adder (650) to the common bus (500) for storing in the memory (300). The motion compensation device of claim 2, wherein the input buffer is implemented to process pixel data in one of a block unit and a unit of 12 pixel input / 9 pixel output unit. The motion compensation device of claim 1, wherein the output buffer is configured to process the pixel data in any one of a field unit or a unit of 2 pixel input / 12 pixel output unit.

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