KR0124167B1 - Half pixel motion compensation circuit in image decoder - Google Patents

Abstract

The present invention relates to a half-pixel motion compensating circuit for a video decoder which can perform efficiently half-pixel motion compensation by using a buffer of small capacity. This circuit includes an inverse differential pulse code modulating part (400) producing a restored frame data; an address generating part (420) producing an address signal for positioning a macro block to be currently processed; a memory (44) storing the frame data from the part (400) and producing the held data as a previous frame data in response to the address signal; and a half-pixel motion compensating part (460) receiving the previous frame data from the memory (400) and producing a predicted frame data half-pixel motion compensated.

Description

Half-Pixel Motion Compensation Circuit in Video Decoder

1 is a block diagram showing a half-pixel motion compensation circuit in a conventional video decoder.

2 is an example diagram illustrating a frame configuration.

3 is a diagram showing a data processing procedure of a macroblock stored in a memory section constituting a conventional half-pixel motion compensation circuit.

4 is a block diagram showing a half-pixel motion compensation circuit in an image decoder according to the present invention.

5 is a diagram showing a data processing procedure of macroblocks stored in a memory section constituting a half-pixel motion compensation circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

100, 400: inverse pulse code modulator 120, 420: address generator

140 and 440: Memory unit 160 and 460: Half pixel motion compensation unit

480: buffer section

The present invention relates to a half pixel motion compensation circuit in an image decoder. In particular, the present invention relates to a half pixel motion compensation circuit that can perform half pixel motion compensation cheaper and simpler using a smaller buffer. It is about.

In devices that process images such as high definition television (HD TV), video telephones, and the like, since video signals have a wider bandwidth than audio signals, a large amount of data is generated when trying to process them digitally. However, the bandwidth available to transmit it is limited, so data must be compressed to transmit it.

Various techniques for effectively compressing data for transmitting digital image signals have been proposed. Commonly used compressor methods include a transform coding method for reducing intra-frame correlation such as discrete cosine transform, and an inter-frame motion compensation predictive encoding method for reducing temporal correlation between frames by using motion compensation.

In this case, motion compensation refers to a motion vector of a previous frame (or field) by estimating the degree of motion of an object in a video signal processing using a predetermined algorithm, that is, a pixel of the current frame in a motion video signal ( Or a block of pixels) by a vector amount indicating in which direction and how far the previous frame moved.

The inter-frame motion compensation predictive encoding method is an image compression method that encodes using the above-described motion compensation, and compares a previous frame and a current frame to estimate how much the image of the current frame is moved in which direction compared to the image of the previous frame. Motion compensation is performed using the motion vector and the previous frame, and the discrete signal obtained by subtracting the motion compensated signal from the signal of the current frame is discrete cosine transform (DCT), quantization, and variable length coding (VLC). Compression coding by Lenght Coding). At this time, subtracting the motion compensated signal from the signal of the current frame is called differential pulse code modulation (DPCM). Accordingly, the receiver compensates for the motion of the previous frame signal and the motion vector by inverse differential pulse code modulation and decodes the current frame signal by adding it to the differential signal.

By the way, motion compensation is generally performed in pixel units, but in order to obtain a more accurate motion vector, it is performed in units of half pixels. However, the half-pixel motion compensation method is not easy in system implementation.

FIG. 1 is a block diagram showing a half pixel motion compensation circuit in a conventional video decoder. The IDPCM unit 100, the address generator 120, the memory unit 140, and the half pixel motion compensation unit 160 are shown in FIG. It consists of. The compressed coded signal transmitted from the encoder passes through a variable length decoder (VLD), an inverse quantization (IQ), an inverse discrete cosine transform unit (IDCT), and the like in the decoder. In addition, the data provided from the IDCT unit (not shown) and the data provided from the half-pixel motion compensation unit 160 are added to transmit the restored data to the display unit (not shown) and the memory unit 120. The memory unit 120 stores the data provided from the IDPCM unit 100 and provides the stored data to the half-pixel motion compensation unit 140 in response to the address signal provided from the address generator (not shown). The half-pixel motion compensator 160 outputs data obtained by performing motion compensation in response to the motion vector transmitted from the encoder (not shown) to the IDPCM unit 100.

2 shows an example of the frame configuration. Pixel refers to a sample when sampling an image signal for digital signal processing, and is a minimum unit that decomposes or constructs a spatial image. Without limiting the invention, one frame consists of 720 pixels on the horizontal axis and 320 pixels on the vertical axis.

A black is a set of pixels and is often used as a basic unit for processing image encoding, motion estimation, and the like. In the present invention, an example block includes 8x8 pixels.

In this case, the half-pixel motion compensator 140 should read more pixels than the pixel-by-pixel motion compensation. That is, in order to process one block of data, nine pixels are read in the horizontal and vertical directions, and eight pixels for calculating the average of two neighboring pixels are output. Therefore, the operation speed of the memory unit 120 is shown as an IDCT unit (not shown). There is a problem that the data output from the data is slower than the output speed.

In order to solve the problem caused by the inconsistency between the data output speed from the IDCT unit (not shown) and the data processing speed in the memory unit 140, the data output to the IDCT unit (not shown) can be temporarily stored. A method of providing data at a data processing speed in the memory unit 140 by providing a buffer has been proposed. In this case, the problem of horizontal half-pixel motion compensation can be solved by increasing the operation speed of the frame memory. However, in the vertical direction, if the operation speed of the memory is increased, the operation speed of the memory itself is too high. If the operation speed is slowed by the amount corresponding to the vertical direction, the buffer capacity at this time is about one eighth of one frame memory. This is a very large capacity, which is a price increase in the implementation of systems such as HDTV.

3 is a diagram illustrating a data processing procedure of macroblocks stored in a memory unit in a conventional half-pixel motion compensation method. One macroblock is composed of four blocks, and each block is composed of eight lines. Is composed of 8 x 8 pixels. The numbers shown in Fig. 3 are line numbers given in line processing procedures. For processing of half-pixel motion compensation in the horizontal direction, data adjacent to the horizontal direction and the vertical direction is always read and processed in addition to the data of the current processing block. Therefore, for the half-pixel motion compensation of a macro block, as shown in FIG. 3, lines in neighboring macro blocks are read together horizontally and vertically, so that 68 clocks are required instead of 64 clocks.

As described above, the IDCT unit (not shown) continuously processes one macro block at a speed of 64 clocks and outputs data, and the memory unit 140 processes at a speed of 68 clocks. The amount of data that the buffer should store accumulates in one frame. Therefore, in order to process all one frame, the capacity of the buffer must be very large, which has a big problem of raising the price of a video system such as HDTV.

Accordingly, an object of the present invention is to provide a half pixel motion compensation circuit which can perform half pixel motion compensation cheaper and simpler using a small capacity buffer in an image decoder.

In order to achieve the above object, an inverse difference pulse code modulator which adds transformed decoded difference data and predictive frame data and outputs reconstructed frame data, and a position of a macroblock to be currently processed in response to a motion vector provided from an encoder. An address generator for generating an address signal for designating the signal; and frame data provided from the inverse difference pulse code modulator; and storing the frame data stored in response to the address signal as macro frame units as previous frame data. Half pixel motion compensation of an image decoder having a memory unit for outputting and a half pixel motion compensation unit for receiving previous frame data from the memory unit and outputting half pixel motion compensated prediction frame data in response to a motion vector transmitted from an encoder Circuitry said memory The pixel data of the block constituting the macroblock designated by the address signal and the pixel data of the region required for half-pixel motion compensation of the designated macroblock are sequentially output line by line, and the data provided from the half-pixel motion compensation unit And temporarily storing the buffer unit and outputting the buffer unit to the reverse differential pulse code modulator.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram showing a half-pixel motion compensation circuit in the image decoder according to the present invention, wherein the IDPCM unit 400, the address generator 420, the memory unit 440, and the half-pixel motion compensation unit 460 are shown. And a buffer unit 480.

The operation of the half-pixel motion compensation circuit in the image decoder according to the present invention configured as described above will be described in more detail.

First, the encoded difference signal and the motion vector transmitted from the encoder of the transmitter are input to the decoder of the receiver. At this time, the difference signal is input to the IDPCM unit 400 after a transform decoding process such as variable length decoding, inverse quantization, and inverse discrete cosine transform.

The IDPCM unit 400 adds the transform-decoded difference data input as described above and the motion prediction frame data output from the half-pixel motion imager 460 temporarily stored in the buffer unit 480 and then provided, thereby restoring the frame. Print the data. The recovered frame data output from the IDPCM unit 400 is provided to the display unit (not shown) and the memory unit 440. The memory unit 440 stores the frame data provided from the IDPCM unit 400. At this time, the address generator 420 generates an address signal for designating a macroblock to be currently processed in response to the motion vector provided from the encoder. Therefore, the memory unit 440 outputs a macro block at a position corresponding to the address signal among the stored frame data.

FIG. 5 is a diagram illustrating a data processing sequence in a memory unit 440 constituting a half-pixel motion compensation circuit according to the present invention. Macro blocks, blocks, and lines are illustrated in FIG. If a macro block to be processed currently is designated in response to an address signal provided from the address generator 420, the data in the designated macro block is output line by line in a predetermined order. The preset order is indicated by numbers in the drawings. At this time, as shown in FIG. 5, line 2 is required to compensate for half-pixel motion in the horizontal direction of line 1, and adjacent macro blurring is required to compensate for half-pixel motion in the horizontal direction of line 2. Line 3 present is required. Therefore, lines 1, 2, and 3 are output sequentially. Therefore, unlike the related art, the line 2 can be processed continuously without delay.

In this manner, the following line-by-line data processing is performed. And, for the half-pixel motion compensation in the vertical direction, the next line of the current processing line is required. Therefore, at least one line of macro blocks neighboring in the vertical direction, that is, lines 49, 50, and 51, is required for vertical half-pixel motion compensation of one macro block.

As described above, the data output from the memory unit 440 is provided to the half-pixel motion compensator 460, and the half-pixel motion compensator 460 is a conventional method known in response to the motion vector transmitted from the encoder. Predictive frame data is output by the method.

As a result, in each of the memory unit 440 and the half-pixel motion compensation unit 460, processing of one macro block is completed within 51 clocks. However, one macro block in the IDCT unit (not shown) is processed at 64 clocks. Therefore, even if the process is completed at 51 clocks in the memory unit 440, 13 clocks should be rested to achieve 64 clocks in order to match the speed with the IDCT unit (not shown). For this purpose, a small capacity buffer unit 480 is provided between the IDPCM unit 400 and the half-pixel motion compensation unit 460. The capacity of the buffer unit 480 is sufficient to be about two macro blocks. In other words, the capacity of two macro blocks is used. When data is recorded in one part, data is outputted in another part, and the roles of the next macro block are exchanged.

As described above, the data outputted from the buffer unit 480 in 64 clock cycles are provided to the IDPCM unit 400 to be combined with the converted decoded signal to form the recovered frame data.

Therefore, the half-pixel motion compensator in the image decoder according to the present invention can efficiently perform half-pixel motion compensation using a buffer having a very small capacity compared to the buffer used in the conventional half-pixel motion compensation circuit. There is an advantage.

Claims (1)

An inverse difference pulse code modulator 400 which adds the transformed decoded difference data and the predicted frame data and outputs the reconstructed frame data, and an address for designating a position of a macroblock to be processed currently in response to a motion vector provided from an encoder The address generator 420 for generating a signal and the frame data provided from the inverse difference pulse code modulator 400 are stored, and the frame data stored in response to the address signal is stored in a previous frame in macroblock units. Memory unit 440 for outputting as data, and half-pixel motion compensation unit for receiving previous frame data from the memory unit 440 and outputting half-pixel motion compensated prediction frame data in response to a motion vector transmitted from an encoder. A half-pixel motion compensation circuit of a video decoder having a number 460, wherein the memory The unit 440 sequentially outputs pixel data of a block constituting the macroblock designated by the address signal and pixel data of an area required for half-pixel motion compensation of the designated macroblock, line by line, and the half-pixel motion compensation unit. And a buffer unit (480) for temporarily storing data provided from (460) and outputting the data to the inverse difference pulse code modulator (400).