KR20010011309A - Algorithm and Implementation Method of a Low-Complexity Video Encoder - Google Patents

Abstract

PURPOSE: A device and a method for low complexity of motion picture encoder are provided to apply to various fields, and to substitute hardware for software to be easily implemented. CONSTITUTION: If a video signal through an NTSC(National Television Standards Committee) decoder(1) is converted with scanning by the block and delivered, an Inter/Inter decision unit(3) decides encoding to intra or inter for each macro block. A DCT(Discrete Cosine Transform) unit(4) converts a coefficient for conversion for the macro block into a frequency coordinate. A quantizer(5) transposes amplitude into a positive number value, for outputting. A variable length coder(6) outputs length proportioned to an algebra absolute value of appearance frequencies through a buffer in a compressed video signal. An Intra/Inter decision unit(10) decides encoding of Intra or Inter, for the macro block fed-back through a dequantizer(8) and an inverse DCT unit(9) from the quantizer(5). A motion estimation and compensation unit(12) estimate motion vector while storing the video signal in a frame memory by the one frame, and compensates the estimated motion vector. A motion compensation/motion non-compensation decision unit(13) decides whether to apply motion compensation for the video signal delivered to the motion estimation and compensation unit(12).

Description

Low complexity video encoder device and method {Algorithm and Implementation Method of a Low-Complexity Video Encoder}

TECHNICAL FIELD The present invention relates to a low complexity video encoder device and a method for implementing the same. In particular, a low complexity video encoder that can be applied to many applications, can be implemented at low cost, and designed to be easily implemented by replacing software parts with hardware. An apparatus and method are provided.

It is well known that the research and development of digital multimedia systems such as video conferencing / telephone, digital VCR, digital video disc (DVD), digital camera, surveillance and security system are actively underway.

In such a multimedia system, in order to reduce the time and path required for signal transmission, or to reduce the capacity when storing a video signal, an implementation technique of compressing a video signal (especially an encoder) is very important.

Compression standards for video signals include H.261 for video conferencing using ISDN networks, H.263 for video telephony using PSTN, MPEG-1 for multimedia using digital storage media (DSM) such as CD-ROM, The standardization of the current TV standard and MPEG-2 for HDTV broadcasting is completed.

In developed countries, according to this trend, a lot of investment is being made in the development of digital video appliances such as digital VCRs and digital cameras.

ITS (Intelligent Transportation System) is actively being developed at home and abroad to control various traffic conditions including road traffic conditions and road conditions using visual information.In addition, PSTN, ISDN, Broadband The situation is being spurred at home and abroad to develop video conferencing / telephone system and video communication system through B-ISDN.

Video signal compression-related components, especially video encoders, are essential for such image-related digital multimedia systems. Until now, they have been developed mainly for video decoders applied to receivers at home and abroad.

Recently, a leading foreign company has developed a DSP (Digital Signal Processor) that can implement MPEG-1 video encoders, but it has been difficult to spread in terms of implementation difficulty, price, and integration.

Therefore, it is necessary to develop a video encoder that can be implemented as a single chip and applicable to various purposes. Therefore, C-Cube Co., Ltd. introduced CL-4110, a processor that can implement a video encoder. The company implemented and commercialized the MPEG-1 Encoder board.

In addition, Array Inc. in the United States is developing a similar processor to promote commercialization.

However, the chips for implementing the conventional video encoder as described above have a disadvantage in that a lot of difficulties arise in implementation because software must be developed together when operating hardware.

Accordingly, an object of the present invention is to provide a multipurpose low complexity video encoder device and method which can be applied to many applications and can be implemented at low cost.

It is another object of the present invention to design so that it can be easily implemented by replacing the software portion with hardware.

In order to achieve the above object, the present invention provides an intra / inter selection for determining the encoding of intra or inter for each macro block when a video signal from an external device is converted into a block-by-block scanning in the format converter. Wealth,

The macroblock is transformed into a code having a length that is proportional to the absolute value of the logarithm of the frequency of appearance received through a discrete cosine transform unit for transforming coefficients for transformation into frequency coordinates and a quantization unit for converting amplitudes into integer values. A variable length encoder for outputting a video signal through a buffer;

An intra / inter selector for determining an encoding of intra or inter with respect to a macroblock returned from the quantization unit through an inverse quantizer and an inverse discrete cosine transform unit;

A motion estimating and compensating unit for estimating a motion vector and compensating for the same while storing the video signal in a frame memory in units of one frame;

The motion compensation / motion security selectors that determine whether to use motion compensation for the video signal transmitted to the motion estimation and compensation unit can be applied to many applications and can be implemented at low cost.

1 is a block diagram showing the overall configuration of the present invention.

2 is a schematic diagram showing sampling of a format conversion unit of the present invention.

Figure 3 is a schematic diagram showing the determination criteria of the intra / inter selection unit of the present invention.

4 is a schematic diagram showing an example of the MFSS of the present invention.

Figure 5 is a schematic diagram showing the determination criteria of the motion compensation / motion security of the present invention.

Figure 6 is a block diagram showing the overall configuration according to an embodiment of the present invention.

7 is a block diagram showing a configuration of a DRAM memory according to an embodiment of the present invention.

8 is a timeline diagram illustrating operation of the DRAM memory.

9 is a block diagram showing a configuration of a motion estimation unit according to an embodiment of the present invention.

10 is a block diagram illustrating a configuration of a processor element according to an exemplary embodiment of the present invention.

11 is a block diagram showing a configuration of a processor array according to an embodiment of the present invention.

12 is a block diagram showing a configuration of a motion compensation unit according to an embodiment of the present invention.

13 is a block diagram showing a configuration of a motion compensation unit of U / V data according to an embodiment of the present invention.

14 is a timeline diagram illustrating an operation of performing motion compensation according to an embodiment of the present invention.

15 is a block diagram showing a configuration of an ITF unit according to an embodiment of the present invention.

16 is a block diagram showing a configuration of a variable length encoder according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1, 21: NTSC decoder 2: format converter

3, 10: intra / inter selector 4, 26: discrete cosine converter

5, 27: quantizer 6, 28: variable length encoder

8,29: inverse quantization unit 9, 30: inverse discrete cosine transform unit

11: frame memory 12, 25: motion estimation and compensation unit

22: interface unit 24: ITF unit

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows an overall configuration of a video encoder according to an embodiment of the present invention.

An NTSC decoder 1 for outputting a signal corresponding to the combination with respect to a combination of NTSC video signals input from the outside,

8x8 or 16x16 block input of raster scanning while converting the 4: 2: 2 Y / U / V format input image of the video signal input from the NTSC decoder 1 into 4: 2: 0 Y / U / V format A format converter 2 for converting the units to scanning;

Intra / Inter Decision (3), which determines the encoding of intra or inter for the macroblock consisting of only I pictures and P pictures according to the size of the GOP from the format converter 2; ,

A discrete cosine transformer 4 for easily converting coefficients for transformation of the macroblock of the video signal from the intra / inter selector 3 into values of a cosine function and converting them into frequency coordinates;

A quantization unit 5 for converting the waveform of a continuous curve into a stepped waveform for the video signal converted into the frequency coordinates transmitted from the discrete cosine transform unit 4 and converting the amplitude into an integer value in units of appropriate levels and outputting the result; ,

A variable length that is output through the buffer 7 as a compressed video signal while allocating a code having a length proportional to the absolute value of the logarithm of the frequency of appearance of the stepped waveform transmitted from the quantization unit 5 to the value. The encoder 6,

An inverse quantization unit 8 for reducing and outputting an integer value of a level unit transmitted from the quantization unit 5 to a video signal having frequency coordinates;

An inverse discrete cosine transformer 9 for reducing the video signal of the frequency coordinate which is the value of the cosine function transmitted from the inverse quantizer 8 to the original video signal;

An intra / inter selector 10 for determining the encoding of an intra or an inter for a macro block of a video signal transmitted from the inverse discrete cosine transform unit 9,

A frame memory 11 for storing and outputting a video signal transmitted by the inverse discrete cosine converter 9 through the intra / inter selector 10 in units of one frame, and

The NTSC decoder 1 estimates a motion vector with respect to the video signal input through the format converter 2 and the video signal transmitted in the frame memory 11 and then compensates for the motion vector. A motion estimating and compensating unit 12 for transmitting to the intra / inter selector 3 of

The motion estimation / motion security compensation selectors 13 determine whether to use motion compensation for the video signal transmitted to the motion estimation and compensation unit 12.

In general video encoders, the compression method can be divided into temporal and spatial compression parts which are largely lossy compression and variable length encoding part which is lossless compression. The spatial compression method is similarity between spatially existing images using discrete cosine transform and quantization. In the temporal compression method, the temporal compression method is very similar because the time difference between two adjacent images is short. Therefore, the similarity is found using the motion estimation and the motion compensation method, and the difference is only transmitted. .

The final compressed image is output to the two compression methods by using the variable length coding method. In the variable length coding, a short code is assigned to a value having a high probability of generating data and a long code is assigned to a value having a low probability of occurrence. It is a compression method to reduce the average code length.

The video signal, which is an input image of 4: 2: 2 Y / U / V format, input to the video encoder which is the video encoder of the present invention through the NTSC decoder 1, is shown in FIG. It will convert to 4: 2: 0 Y / U / V format and also convert the input of raster scanning to scanning in 8x8 or 16x16 blocks.

The converted input is determined by the encoding mode and the size of the GOP (Group of Picture). The type of the picture consisting of only I and P pictures is determined.

If the picture type is intra, all macroblocks in the picture are encoded intra and are encoded through discrete cosine transform, quantization, and variable length incubation.

When the type of the picture is an inter (P picture), the macroblock in the picture may be encoded intra or inter.

First, after calculating the motion vector by the motion estimation for the input image, it is determined whether to use the motion compensation by using the reconstructed image and SAD (Sum of Absolute Difference). The result is compared with the variance of the reconstructed block and the variance of the encoding macroblock to determine whether to encode into an intra macroblock or a non-intra macroblock.

In case of intra macroblock, encoding is performed through discrete cosine transform, quantization, and variable length coding. In case of non-intra macroblock, difference between reference macroblock of previous frame is encoded using discrete cosine transform, quantization, and variable length coding. .

The encoded image decodes the signal output from the quantization unit 5 in the reverse order of encoding and stores it in the frame memory 11 for use as a reference image of the non-intra picture.

Since the B picture is not used, only the image of the previous one frame needs to be stored.

The variable length encoder (VLC) 6 performs coding by using a code book defined in the MPEG standard.

Intra / inter selector (3) 10, which receives the macroblock in the format converted state from the format converter 2, can selectively encode the macroblock of the P picture intra or non-intra. The result obtained by the motion estimation and compensator 12 and the motion compensation / motion security compensation selector 13 is compared with the efficiency when encoding into an intra macroblock to select a higher coding efficiency.

The method used in this embodiment is determined by comparing the variance of the current macroblock with the variance value of the current macroblock and the motion-compensated macroblock from the previous image. As shown in FIG. The non-intra (non intra) and the diagonal line connecting the intersection of VAR 256 and VAROR 256 at the intersection of VAR 64 and VAROR 64 is the baseline for selecting inter and intra.

Discrete Cosine Transform (DST) 4 and Inverse Discrete Cosine Transform (IDST) (9) for receiving a picture that is selectively encoded from the intra / inter selector (3). Reduces the redundancy in two-dimensional space.

The discrete cosine transformer 4 divides a picture into 8 x 8 blocks by a method of removing correlation of data through two-dimensional axis transformation, and the converted data are biased into a low frequency band. In (5), spatial compression is performed by removing high frequency components while quantizing.

The formal expression of the discrete cosine transform unit 4 and the inverse discrete cosine transform unit 9 used in the present embodiment is expressed by the following equation (1).

In the data obtained by the discrete cosine transform unit 4, information is centered on low frequency, and since the characteristics of the human visual system (HVS) are sensitive to low frequency components rather than high frequency components, the quantization unit 5 uses these characteristics to obtain frequency. By dividing different weights according to the components, high-frequency components can be removed and a large compression effect can be obtained with a small loss.

The algorithm of the quantization unit 5 applied in the present embodiment is as follows.

That is, when the macroblock type is intra, the quantization unit 5 and the inverse quantization unit 8 divide the DC coefficient and the AC coefficient and perform the following equation (2).

The DC coefficient represents the average brightness of the screen and is the most sensitive to the human eye, and is quantized to a fixed value of 8 to reduce loss. The AC coefficient is quantized by a quantization matrix and a quantization step value.

In the case of the inter (non-intra) macroblock, the value is a difference between the motion compensated image and the same operation is performed regardless of the DC and AC coefficients as shown in Equation (3) below.

Where w (i, j) is the quantization matrix, and the default quantization matrix is shown in the following table.

As for the characteristics of the default intra matrix, the intra is configured to give a large value for the high frequency component which is relatively insignificant and to give a small value for the low frequency component, and the non-intra matrix is composed of the same value.

The video encoder of this embodiment uses only a default quantization matrix.

The motion estimation and compensation unit 12 is a compression method for eliminating redundancy of temporal information in a moving image. The motion of the horizontal vertical component with respect to the block that best matches the current macroblock and the previous image is obtained. Is to find a vector.

The Block Matching Algorithm (BMA) is most commonly used to find the macroblock that best matches the current macroblock in the search area.Full Search (FS) and Hierarchical Search (HS) are used for the Block Matching Algorithm. , TSS (Three-Step Search), FSS (Four-Step Search) and the like are typically used.

Dual FS has the highest performance but requires a lot of computation, which makes it difficult to implement in real time. HS is the most ideal form of high-speed algorithm, but it is also computational and complex in VLSI, and TSS does not consider statistical motion vectors. In fact, there is an inefficiency in practical applications because all motion vectors are considered equally likely.

FSS, on the other hand, is known to have higher efficiency than TSS without requiring as much computation as FS.

Therefore, the present embodiment uses a Modified Four-Step Search (MFSS) algorithm, which is a modification of the existing FSS algorithm.

The characteristics of MFSS is that the number of search points is slightly higher than that of the existing FSS, but the hardware is easy to implement and sufficient search is possible because it consists of unit modules of base module composed of 9 points with constant interval of search points in each stage. The point distribution has a merit of being much influenced by a lot of movement and littleness and showing a performance close to FS (Full Search).

The searching method of the algorithm of the MFSS is as shown schematically in FIG.

Finding the minimum error point for nine points, including the origin and eight surrounding search points,

Obtaining a minimum error point for three points based on the minimum error point of the previous step,

Here, the distribution of the search points is a point in the range of 3 toward the upper left side of the reference point and 2 toward the lower right side.

Obtaining a minimum error point for 36 points based on the minimum error point of the previous step,

Here, the distribution of the search point is set in a direction in which the distribution of the search point is far from the original point among four points at the center of the distribution.

Finding a minimum error point for nine points including the origin and eight search points around the minimum error point of the previous step,

At this time, the distance between the found point and the origin becomes a motion vector.

The motion compensation / no motion compensation decision unit 13, which receives data obtained by the motion estimation and the motion estimation of the compensation unit 12, moves the data and the motion obtained from the motion estimation. The use of motion compensation is determined by comparing the efficiency of the encoding with the data without compensation.

This compares the error between the macroblock reconstructed by motion compensation and motion reconstruction for the current macroblock and the reconstructed macroblock (if the motion vector is 0) and does not use motion compensation if there is no significant difference. Encoding reduces the occurrence of bits from the transmission of the motion vector.

The determination of the motion compensation / motion security compensation selection unit (MC / No MC) 13 used in this embodiment is a modification of the method proposed by SM3 (Simulation Model 3) to be easily implemented in hardware.

As an error comparison method, SAD was used, and as shown in FIG. 5, the area of motion compensation and the area of motion security included a vertical line of x = 1, an oblique line of y = 2x, a vertical line of x = 1, and an oblique line of y = x. It is characterized by the division of the area distinguished by them.

6 is a block diagram showing a state in which a video encoder is implemented in one chip according to an embodiment of the present invention.

In the interface unit 22 that receives the digital video signal directly from the NTSC decoder 21, it is stored in the DRAM memory 23 that is externally connected and then stored in 8x8 and 16x16 block units, which are video formats required for operation at a system clock speed. Scan and print,

The delay of time according to the operation is not to use a separate delay element, but to adjust the read time from the DRAM memory 23 to minimize the amount of memory required.

The image signal input from the DRAM memory 23 is input to the Inter Frame Processor (ITF) unit 24 to determine the mode of Intra / Inter.

Here, the first frame of the GOP (Group of Picture) is always in the intra frame mode.

Since the motion-compensated image from the moving estimation and compensation unit 25 is also fed back to the ITF unit 24, the variable length coding unit 28 passes through the discrete cosine transform unit 26 and the quantization unit 27. Output through

At the same time, the image reconstructed through the inverse discrete cosine transform unit 29 and the inverse quantization unit 30 (Inverse Quantization) for motion estimation and compensation is stored in the DARM memory 23 frame by frame.

The reconstructed image stored in the DRAM memory 23 is returned to the motion estimation and compensation unit 25 to find a motion vector through a process of motion estimation, and then output the motion compensated data to the ITF unit 24 using the motion vector.

FIG. 7 shows a detailed configuration of the interface unit. Since there are three types of data to be stored in the DRAM memory 23, a storage area for storing them is required, and these control input / output.

That is, CFB (Current Frame Buffer), which is a frame memory for converting video signals input from NTSC decoder 21 into block and macro block formats, and RFB (Reconstructed Frame Buffer) for storing reconstructed video for motion compensation. Finally, the DRAM memory 23 is externally configured to store three kinds of data of CB (Channel Buffer) for storing the compressed bit string.

In this case, since the frame memory has to read and write alternately, it needs memory capacity to store 4 frames, and CB is designed with a first-in first-out (FIFO) structure.

The interface unit 22 generates the necessary synchronization signal while controlling the DRAM memory 23 in order to efficiently input / output the above three memories, and outputs them to other modules constituting the encoder so that the periods of operation coincide. When operating the DRAM memory 23, various image formats are supported and controlled accordingly.

The controller 31, which receives the video signal from the NTSC decoder 21, outputs a synchronization signal (Sync.) While receiving the mode signal and the clock signal, thereby enabling stable internal operation. Let's do it,

Under the control of the controller 31, a CFWB (Current Frame Write Buffer) 32, which receives a video signal from the NTSC decoder 21 and temporarily stores it, converts the block and macro block formats into a DRAM memory 23. Output control signal and address value to save in block unit)

The current frame read buffer (CFRB) 33 under the control of the controller 31 controls a control signal and a address value for reading a video signal stored in the DRAM memory 23 in block and macro block formats. Output it,

Reconstructed Frame Write Buffer (RFWB) 34 receiving and temporarily storing a video signal of a frame unit restored from the inverse discrete cosine transform unit 29 while being controlled by the controller 31 is used for motion compensation. Generating a control signal and a address value for storing the restored frame image in the DRAM memory 23,

The Reconstructed Frame Read Buffer (RFRB) 35 under the control of the controller 31 outputs a control signal and a address value for reading a video signal stored in the DRAM memory 23 on a frame basis. ,

After the motion compensation is completed in the motion estimation and compensation unit 25, the CB (Channel Buffer) 36, which sequentially stores the compressed bit strings from the variable length encoder 28 and sequentially outputs them, reads them at a desired speed and outputs them. It outputs control signal and address value.

The interface 37 receiving information corresponding to the control signal and the address value from the controller 31, the CFWB 32, the CFRB 33, the RFWB 34, the RFRB 35, and the CB 36 has various forms. A control signal (Address, Data, RAS, CAS, OEN, WEN, etc.) that can be directly connected to the DRAM memory 23 is output while controlling to perform a desired function in accordance with the mode of.

Here, the memory mapping of the DRAM memory 23 varies according to the input video format. In order to support the data described above, the DRAM memory 23 divides the bandwidth for accessing the DRAM memory 23 through time-sharing. Used.

At this time, Fast Page / Hyper Page Mode was used among the supported modes of the DRAM memory 23 in order to increase the utilization efficiency of the DRAM memory 23, and the CFWB 32, CFRB 33, RFWB 34, RFRB 35 and The operation of the CB 36 is time-divided, and FIG. 8 shows time diagrams of control signals (Address, RAS, LCAS, UCAS, WEN, OEN, wData, rData) output from the interface 37 to the DRAM memory 23. FIG. Indicated.

Here, the timing for the CB 36 uses the timing of the RFWB 34 and the RFRB 36 during the blanking period in which the image data is not valid.

9 is a block diagram showing an overall structure of a motion estimation unit to which the MFSS algorithm described above is applied.

A SW memory 41 for storing data of a search area,

DB memory 42 for storing data of the reference macro block,

A memory controller 43 which controls data input / output of the SW memory 41 and the DB memory 42;

A processor array 44 comprising nine process elements for calculating a sum of absolute difference (SAD) value for a base module consisting of nine search points,

PMVG 45 for obtaining the position of the minimum value among the nine SAD values obtained by the control array 44,

The memory controller 43, the processor array 44, and the MEP controllers 46 which obtain final motion vectors while controlling the internal operations of the PMVG 45 are configured.

The memory controller 43 is input with SW, which is a data input of a search region, DB, which is a data input of a reference macro block, and START, a start signal of motion estimation.

The memory control unit 43 and the MEP controller 46 simultaneously input NNEX, which is an input synchronization signal of the SW and DB,

The MEP controller 46 receives a BND_SIG, a clock CLK, and a reset RESET indicating that the search area spans the screen edge.

FIG. 10 is a diagram showing the configuration of nine control elements for applying a method for the motion estimation to compute 32 bits, that is, four pixels simultaneously.

An error that obtains an absolute difference when the enable signal PE-E is received from the second delay element 51 with respect to the previous frame data transmitted through the first delay element 50 and the current data. Detectors 52, 53, 54, 55,

Adders 56 and 57 that sum the error values of the error detectors 52 and 53 and 54 and 55,

An adder 58 that adds the added values of the adders 56, 57, and

The accumulator 59 accumulates the addition value of the adder 58 and outputs a control element output value PEOUT.

FIG. 11 is a diagram illustrating a configuration of a processor array including nine control elements.

The control element output values PEOUT0 to PEOUT8 of the first to ninth unit control elements PE0 to PE8 are mixed in the multiplexer MUX to output the SAD.

The reason why the control array 44 is composed of nine unit control elements PE0 to PE8 is that the search points constituting the MFSS algorithm are divided into nine units.

When the SAD values are calculated in the nine unit control elements PE0 to PE8, the multiplexer MUX is connected to the output terminals of the unit control elements PE0 to PE8 in order to output the SAD values in the order of comparison. do.

MEP controller 46 controls the overall operation of the motion estimator. Some of the important tasks are summarized as follows.

First, the data read start signal and the read start address of the SW are input to the memory controller 43 to read the SW and DB for calculating the minimum error points for the nine search points constituting the base module. Create

Second, a signal indicating the final output position of the nine unit control elements PE0 to PE8 is generated.

Third, PMVG generates a synchronization signal for comparing the minimum value for the nine output values.

In this way, when the motion vector is calculated through the final stage of motion estimation, the motion estimation synchronization signal mc_sync and the control signals mvx and mvy are output.

As a whole, the operation control of the MEP controller 46 consists of an internal counter, which starts in synchronization with the start signal and is reset when the final motion vector is output.

The overall operation sequence is to increase the step counter from 0 to 3 according to the steps of the MFSS algorithm, and to increase the sub step counter from 0 to 3 to perform the base module unit operation for each step counter value.

Each time the substep counter changes, the minimum error values in the base module are compared and the memory control section 43 informs the start address of the data to be read.

12 illustrates an internal configuration of a motion compensator,

Motion Compensation_Y (MC_Y) 61 for motion compensation on the Y image,

MC_UV 62 which is a motion compensation portion for U and V,

The MC_MUX 63 outputs data MCed compensated for the motion output from the MC_Y 61 and the MC_UV 62.

The compensation data SWY0, SWY1, SWY2, and SWY3 for Y are input to the MC_Y 61, and MV_SYNC, which is a synchronization signal for outputting SW and motion vectors, is input to the SW data input for U and V images to the MC_UV 62. MVX and MVY, the motion vectors, and STARTs indicating the start of motion compensation are inputted.

The MC_MUX 63 receiving the data compensated by the MC_Y 61 and MC_UV 62 outputs the last motion compensated data Mced.

Here, since the motion compensation for Y is the data of the macroblock corresponding to the last search point of the last step of the motion estimator, the motion compensation image is received and the output format is adjusted and output.

The color image is composed of contrast information (Y: Luminance) and color information (U, V: Chrominance). In motion estimation, only the Y component is applied.

Of course, it does not need to be done for U and V because contrast information moves with it.

However, motion compensation should be applied to Y, U, and V images respectively. If Y, U, and V are sampled at 4: 2: 0, the application of motion vectors may be different.

That is, the 4: 2: 0 configuration of an image means that if there are four Y pixels in the screen, there are two U and V colors for color information, and when applied to a motion vector, the motion vectors in U and V are applied. It can be seen that must be half of the motion vector of Y.

Therefore, the motion vectors of U and V may be divided by two.

The motion compensation of the motion estimation and compensation unit 25 has a form in which the same structure is shared with each other since the motion compensation method for Y and the motion compensation method for U and V are the same.

13 shows a configuration according to an embodiment of a motion compensation method for U and V,

U_SW memory 64 for storing data of U video,

A V_SW memory 65 that stores data of a V video,

MCUV_R (Motion Compensation Read Control of U, V) 66, which controls reading to compensate motion for U and V images,

MCUV_W (Motion Compensation Write Control of U, V) 67 which controls writing to compensate for motion on U and V images,

Outputs data MCed whose motion is compensated while interpolating signals while inputting / outputting data of the U_SW memory 64 and the V_SW memory 65 to the control signals from the MCUV_R 66 and the MCUV_W 67. MCUV_NFT (68).

The MCUV_R 66 receives MV_SYNC, which is a synchronization signal of a motion vector output, MVX and MVY, which are motion vectors, and STARTs for starting motion compensation,

The MCUV_W 67 receives a START signal indicating the start of motion compensation and a control signal MCU_W_ST.

The MCUV_NTF 68 performing compensation by interpolation while receiving control signals from the MCUV_R 66 and the MCUV_W 67 outputs the last motion compensated data Mced.

On the other hand, the motion compensation operation is a process of outputting Y image data after outputting Y image data and outputting U image data after outputting Y image data as shown in FIG. Repeat this.

The operation is changed when the control signals (STSRT, MCU_W_ST, MCU_ST, MCV_ST) for these operations are input.

U / V motion compensation reduces the size of the memory by half because the data is stored in SW and the reading time for motion compensation does not overlap.

FIG. 15 illustrates a configuration of the ITF unit described with reference to FIG. 6.

Intra-frame mode and inter-frame mode are used in the intra-inter mode and inter-frame mode in the intra / inter selector 71 that receives the 8x8 block-predicted frame inputted with motion compensation and the current frame inputted in the DRAM memory 23. Determine the mode in blocks.

One macroblock period is required for intra / inter decision, which is compensated for through the first-in first-out buffer (FIFO1) 72 and the second-in first-out buffer (FIFO2) 73, respectively. .

The input image compensated for the delay outputs current frame data from the MUX_SUB 74 in the intra-frame mode and discretely divides the difference between the two inputs in the inter-frame mode. The cosine transform unit (DCT) 26 outputs the result.

In addition, MUX_ADD after compensating for the delay of the image inputted from the inverse discrete cosine transform unit 30 and the predicted frame image through the third first-in first-out buffer (FIFO3) 75 and the fourth first-in-first-out buffer (FIFO4) 76. It is input to 77.

In the intra frame mode, the image input from the inverse discrete cosine transform unit 30 is output. In the intra frame mode, the image compensated by the sum of the two input images is output to the reconstructed frame buffer of the DRAM memory 23.

16 illustrates a configuration of a variable length encoder.

In order to calculate the run and length of the discrete cosine transform coefficients (DCT Coefficients) transmitted from the quantization unit 27 of FIG. 6, an 8x8 block time is required. (FIFO 5) 81,

A run length coder 82 for calculating the above run and length,

A header coder 83 for generating other Syntax Data, Header, etc. in addition to the above coefficients;

A multiplexer (MUX) 84 for selecting run and length of the coefficients and other headers,

A variable length code code generator (VLC Code Generator) 85 for reading codebook information stored in a ROM 86 from the above information and generating a final code;

32-Bit Parker (87) that bundles the generated variable-length code in 32-bit units, and

It consists of controllers 88 that control the multiplexing so that the processing of data conforms to the MPEG Syntax structure while controlling the operations of the run length coder 82, the header coder 83, and the multiplexer 84.

In particular, the header signals of the upper layer of the sequence, the GOP, and the picture level generate and multiplex the code during the vertical blanking period.

The header information of the slice layer is generated and multiplexed during the horizontal blanking period, and the header information (Quant, Motion Vector, MBA, CBP, ..) of macro block units is the macro block. The period is allocated seven 8x8 block periods to be processed during the blanking period of one block.

The main codebook is stored as a lookup table in the ROM 86. The format to be stored is to separate and store different codebooks, and then input an address of data for coding. Information about the codebook output from is stored as follows.

When using the ROM 86 having a width of 16 bits, the 16 bits are divided into 6 bits and 10 bits, respectively.

In this case, 6 bits are code length information indicating a code length, and the remaining 10 bits are actual code information.

If all codes are 5 bits or more in length, the first part of the preceding code always starts with 0. Therefore, the code length is first interpreted using 16 bits read from ROM 86, and then the code length exceeds 10 bits. In that case, just fill in with zeros before it.

This is exactly what the variable length code code generator 85 does.

Since the length of the code output from the variable length code generator 85 is 32 bits maximum and variable, the 32-bit parker 87 fills in 32-bit units and always outputs in 32-bit units.

According to the low complexity video encoder device and method of the present invention, when the video signal from the outside is converted into a block-by-block scanning in the format converter and transmitted from the outside, the intra / inter selector is configured to perform intra for each macro block. Or determine the encoding of the interle,

For a macroblock, the length is proportional to the absolute value of the logarithm of the frequency of appearance in a discrete cosine transform unit for transforming coefficients for transformation into frequency coordinates and a quantization unit for outputting by converting an amplitude into an integer value. Is a video signal compressed with a

The intra / inter selector determines the encoding of intra or inter for the macro block fed back through the inverse quantization unit and the inverse discrete cosine transform unit in the quantization unit.

The motion estimation and the compensation unit for the video signal is stored in the frame memory in units of one frame by the decision of the motion compensation / motion security compensation unit. It can be implemented at low cost.

Claims (7)

Receives a video signal input from the outside as a signal corresponding to the combination through the NTSC decoder (1) and converts the 4: 2: 2 Y / U / V format input image to 4: 2: 0 Y / U / V format A format converter 2 for converting the raster scanning input into 8x8 or 16x16 block unit scanning; According to the size of the GOP from the format converter 2, all of the VAR 64 is inter intra, up to VAR 64 for the macro block including only the I picture and the P picture, and VAR 256 at the intersection of VAR 64 and VAROR 64. An Intra / Inter Decision (3) for determining the encoding of the intra or the inter such that an oblique line connecting the intersection point of the VAROR 256 and the base line selects the inter and the intra; The 8/8 picture is removed in such a manner as to remove the correlation of the data through the 2-D axis transformation while easily calculating the coefficient for transformation of the macroblock of the video signal from the intra / inter selector 3 as the value of the cosine function. A discrete cosine transform unit 4 which is divided into blocks and performed; A quantization unit for converting the waveform of the continuous curve for the video signal converted to the frequency coordinates transmitted from the discrete cosine converter 4 into a stepped waveform while removing the high frequency components, and outputs the amplitude by substituting an integer value of an appropriate level unit ( 5) with, Compute the run and length by delaying the discrete cosine transform coefficients delivered from the quantization unit 5, select the run and length and other headers of the coefficients, and read the codebook information stored in the ROM 86 by the code code generator. After the final code is generated by the parker 87 is bound in 32-bit units and the variable length encoder 6 for outputting through the buffer (7) as a compressed video signal, An inverse quantization unit 8 for reducing and outputting an integer value of a level unit transmitted from the quantization unit 5 to a video signal having frequency coordinates; An inverse discrete cosine transformer 9 for reducing the video signal of the frequency coordinate which is the value of the cosine function transmitted from the inverse quantizer 8 to the original video signal; An intra / inter selector 10 for determining the encoding of an intra or an inter for a macro block of a video signal transmitted from the inverse discrete cosine transform unit 9, The base module is composed of nine points with a constant interval between search points for the video signal input from the NTSC decoder 1 through the format converter 2 and the video signal transmitted from the frame memory 11 in units of 1 frame. Estimating a motion vector with a unit module of a (Base Module) and compensating with a Modified Four-Step Search (MFSS) algorithm that performs compensation for the motion vector to be delivered to the intra / inter selector 3. Compensation unit 12, And a motion compensation / motion security selector (13) for determining whether to use motion compensation for the video signal transmitted to the motion estimation and compensation unit (12). The motion estimation and compensator 12 finds a minimum error point with respect to nine points, including the origin and eight surrounding search points, Obtaining a minimum error point for three points within the range of 3 from the reference point to the top left and 2 from the bottom right to the minimum error point of the previous step; Obtaining a minimum error point for 36 points among the four points at the center of the distribution based on the minimum error point of the previous step, in which the distribution of the search points is set away from the origin point; The MFSS algorithm is performed by estimating the distance between the found point and the origin as a motion vector by finding the minimum error point for 9 points including the origin and the eight search points around the minimum error point of the previous step. Low complexity video encoder device characterized in that the. The apparatus of claim 1, wherein the video encoder receives the digital video signal directly from the NTSC decoder 21, and stores the video encoder in an externally connected DRAM memory 23, and is required for operation at a system clock speed. Scan and output in 8x8 and 16x16 block units, which are video format, The video signal input from the DRAM memory 23 is input to the ITF unit 24 to determine the intra / inter mode. The ITF unit 24 receives a motion-compensated image from the moving estimation and compensation unit 25 and then receives a discrete cosine transform unit 26 and a quantization unit 27 and then a variable length encoder 28. Output via For the motion estimation and compensation, the image reconstructed through the inverse discrete cosine transform unit 29 and the inverse quantization unit 30 (Inverse Quantization) is again stored in the DARM memory 23 frame by frame, The reconstructed image stored in the DRAM memory 23 is returned to the motion estimation and compensation unit 25 to find a motion vector through a process of motion estimation, and then output the motion compensated data to the ITF unit 24 using the motion vector. Low complexity video encoder device composed of one chip. The controller 31 of claim 3, wherein the interface unit 31 receives the video signal from the NTSC decoder 21 and outputs a synchronization signal while receiving a mode signal and a clock signal, thereby enabling internal stable operation. The CFWB 32, which receives the video signal from the NTSC decoder 21 and temporarily stores it under the control of the controller 31, converts it into a block and macro block format and stores it in the DRAM memory 23 in block units. And the address number The CFRB 33 under the control of the controller 31 outputs a control signal and a address value for reading a video signal stored in the DRAM memory 23 in block and macro block formats. Under the control of the controller 31, the RFWB 34 receiving and temporarily storing a video signal of a frame unit restored from the inverse discrete cosine transform unit 29 stores the image of the restored frame for motion compensation in the DRAM memory 23. Generate control signal and address value to save) The RFRB 35 under the control of the controller 31 outputs a control signal and a address value for reading a video signal stored in the DRAM memory 23 on a frame basis. The motion estimation and compensation unit 25 completes the motion compensation and stores the bit stream compressed from the variable length encoder 28 and sequentially outputs the control signal for reading and outputting at a desired speed. Output the address, The interface 37 receiving information corresponding to the control signal and the address value from the controller 31, the CFWB 32, the CFRB 33, the RFWB 34, the RFRB 35, and the CB 36 has various forms. Output control signals (Address, Data, RAS, CAS, OEN, WEN) that can be directly connected to the DRAM memory 23 while controlling to perform a desired function according to the mode of A low complexity video encoder device using Fast Page / Hyper Page Mode among supported modes to support all the data in the DRAM memory 23 whose memory mapping is different according to the input video format and to increase the use efficiency. The method of claim 3, wherein each unit control element for calculating the error in the macro block unit in the motion estimation and compensation unit is a second to the previous frame data and the current data transmitted through the first delay element (50) Absolute Difference is obtained by the error detectors 52 to 55 that receive the enable signal PE-E from the delay element 51. The error values of the error detectors 52, 53, 54, 55 are added by the adders 56, 57 and 58, and the accumulator 59 accumulates the added values to control element output value PEOUT. To print The control element output values PEOUT0 to PEOUT8 of the first to ninth unit control elements PE0 to PE8 are mixed in the multiplexer MUX to output the SAD. The motion compensator compensates for the Y signal by inputting the macroblock for the last search point of the last step from the motion estimator, storing it in memory, converting it to an output format, and searching the U / V using the motion vector estimated for Y. A low complexity video encoder device for performing motion compensation from an area. 4. The Intra-inter selector 71 of claim 3, wherein the ITF receives a Predicted Frame in 8x8 block units inputted with motion compensation and a Current frame in 8x8 block units input from the DRAM memory 23. Determine the mode in macroblock unit between Frame mode and Inter-Frame mode, The period of one macro block for the selection of intra / inter is compensated by the first-in-first-out buffer (FIFO1) 72 and the second-in-first-out buffer (FIFO2) 73, The input image outputs current frame data from the MUX_SUB 74 in the intra-frame mode and outputs the difference between the two inputs to the discrete cosine transform unit (DCT) 26 in the inter-frame mode. The delay of the image inputted from the inverse discrete cosine transform unit 30 and the predicted frame image is also compensated through the third-in-first-out buffer (FIFO3) 75 and the fourth-in-first-out buffer (FIFO4) 76 and then MUX_ADD ( 77), In the case of intra frame mode, an image input from the inverse discrete cosine transform unit 30 is output. In the case of intra frame mode, an image compensated by the sum of two input images is output to the reconstructed frame buffer of the DRAM memory 23. Low complexity video encoder device. 4. The method of claim 3, wherein the variable length encoder is fifth preemptive for delay of an 8x8 block for calculating run and length of discrete cosine transform coefficients transmitted from the quantization unit 27. An election buffer (FIFO5) 81, A run length coder 82 for calculating the above Run and Length, A header coder 83 for generating other Syntax Data, Header, etc. in addition to the above coefficients, A multiplexer 84 for selecting the run and length of the coefficient and other headers, A variable length code code generator 85 for reading the codebook information stored in the ROM 86 from the above information and generating a final code; 32-Bit Parker (87) which bundles the generated variable-length code in 32-bit units and outputs it, The length of the entire code is composed of controllers 88 that control the multiplexing so that the processing of data conforms to the MPEG Syntax structure while controlling the operations of the run length coder 82, the header coder 83, and the multiplexer 84. Is less than 10 bits except 10 at the beginning, and saves, and inputs 32-bit variable length code and outputs 32 bits once when 32 bits are filled.