JP3004763B2 - Video signal multiplex decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal multiplex decoder for a video signal transmission system using an inter-frame difference system.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional video signal multiplex decoding apparatus disclosed in Japanese Patent Application Laid-Open No. 63-27,899. FIG.
, 1a to 1d are encoded data receiving circuits, 2a to
2d is a reception buffer memory for temporarily storing received video encoded data, and 3 is a variable length for reproducing difference information from encoded data to which codes of different lengths are assigned according to the frequency of occurrence of difference information. A decoding circuit 4 is an addition circuit for reproducing the video data of the current frame from the reproduced difference information and the video data of the previous frame that has already been reproduced, and 5a to 5d are for accumulating the reproduced video data of the previous frame. , A video memory for converting the reproduced video signal into an original video signal and temporarily storing the converted video signal, 7 a D / A conversion circuit for obtaining an analog video signal, and 8 to 10 A changeover switch for changing the input coded data to be decoded and the contents of the previous frame for each frame-by-frame decoding process. Address control unit that controls, based on the designation from the decoding control circuit, 12 is a multiple decoding control circuit for controlling the operation of the entire multiplex decoder.

Next, the operation will be described. In FIG. 3, the video coded data input simultaneously is represented by four images, but this value may be an arbitrary integer, and is set to n here. Since there are two possible operation methods, 1), 2)
The items are explained separately.

1), n encoded data receiving circuits 1a to 1
The encoded video data received in 1d is temporarily stored in the corresponding reception buffer memories 2a to 2d.
The multiplex decoding control circuit 12 determines the channel to be decoded while controlling the amount of residual information in each reception buffer memory, and controls each switch 8. The encoded video data read from the corresponding reception buffer memory by the changeover switch 8 is converted into difference information by the variable length decoding circuit 3,
Further, the added image is added to the reproduced video data of the previous frame extracted by the changeover switch 10 by the adding circuit 4, and the video of the current frame is reproduced. The reproduced video data is stored in the frame memories 5a to 5d of the corresponding channel via the changeover switch 9 for the reproduction of the next frame, and the video memory 6 specified by the address control circuit 11 is also stored.
Is written to the address. When the decoding process for one frame is completed in this way, the multiplex decoding control circuit 12 selects the next channel to be decoded, and repeats the same decoding process.

[0005] By the above processing, n is stored in the video memory 6.
A video in which the video of the point is synthesized is created, and is updated as needed in accordance with the decoding process. Further, the output of the video memory 6 is converted into an analog signal by the D / A conversion circuit 7, and the analog signal is output and displayed on the monitor television, so that images at n points can be displayed simultaneously. However, in this device, the coded data receiving circuit, the receiving buffer memory, and the frame memory require n times as many as the case of one input video coded data, and the variable length decoding circuit 3 also requires n times more than the case of one input. Double the processing power is required.

2) In this method, since the screens at the n points are synthesized, the number of pixels is reduced to 1 / n by utilizing that each image has a size of 1 / n. for that reason,
If the number of pixels of the input video is encoded as 1 / n, the amount of generated coded information can be reduced. It is possible to use only the same amount of data as in the case where the number of data is one, and the variable-length decoding circuit 3 also needs only the processing capacity when one input is used.

[0007]

As described above, in the video signal multiplex decoding apparatus shown in FIG. 3, when the method 1) is used, the coded data receiving circuit, the receiving buffer memory and the frame memory are used. Is required n times as large as when there is one input video encoded data, and the variable length decoding circuit also needs n times the processing capacity as compared with the case of one input. Further, when the method 2) is used, there is a problem that it is necessary to notify in advance that the number of blocks on the encoding side should be reduced to 1 / n to perform encoding.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional example, and is based on the capacity of a frame memory required for one input and the processing capability of a variable length decoding circuit.
It is an object of the present invention to provide a video signal multiplexing decoding apparatus capable of processing input video coded data of an arbitrary number of blocks from n points.

[0009]

According to the present invention, there is provided a video signal multiplexing / decoding apparatus according to the present invention, wherein arbitrary video signals transmitted from multiple points are provided.
Before decoding the input video encoded data of the number of blocks
When synthesizing video encoded data for one screen with a synthesis circuit
Of video encoded data sent from multiple locations
When the total number of locks is greater than the number of blocks in the output video
Deletes extra block data,
-Insert the block data to
By matching the number of blocks on the output screen, decoding can be performed by one variable-length decoding device.

[0010]

In the video signal multiplex decoding apparatus according to the present invention, the amount of hardware necessary for one input video encoded data,
The multi-input video encoded data is combined into one screen with the processing capability and decoded.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a diagram for explaining an embodiment of the present invention.
Reference numerals 5 and 7 are the same as those of the conventional apparatus shown in FIG. As a new configuration, reference numeral 13 denotes a screen synthesizing circuit which forms one screen from video coded data from n points, and FIG. 2 shows an example of the screen synthesizing. 2, reference numerals 14a to 14d denote input screen configurations, 15 denotes an output screen configuration, and 16 denotes an output video. Although the number of input video encoded data is shown as 4 in the drawing, this value may be an arbitrary integer, and is described here as n.

Next, the operation will be described. In FIG. 1, the video encoded data received by the n encoded data receiving circuits 1a to 1d correspond to the corresponding reception buffer memories 2a.
.About.2d. The screen synthesizing circuit 13 reads the video coded data from the n-point from the reception buffer memories 2a to 2d with the same frame phase, synthesizes n screens, and converts it into video coded data for one screen. At this time, the screen synthesis circuit 13 has a built-in
Block sent from n point by the screen composition control unit
When the total number of blocks sent from the n point is larger than the number of blocks of the output video, the readout of the reception buffer memories 2a to 2d is performed.
In this case, the control unit controls the output, deletes unnecessary block data in a portion where the screens overlap, and inserts dummy block data when the number is small, thereby making the number of blocks of the composite screen equal to the number of blocks of the output screen.

The encoded coded video data from the picture synthesizing circuit 13 is converted into difference information by the variable length decoding circuit 3 and further added to the reproduced video data of the previous frame by the adding circuit 4 to reproduce the video of the current frame. You. The reproduced video data is stored in a frame memory 5 for reproducing the next frame.
Is accumulated in Further, the video of the current frame reproduced by the adder circuit 4 is converted into an analog signal by the D / A conversion circuit 7 and output, and is displayed on a monitor television, so that the video at n points can be displayed simultaneously. In this way,
The decoding process for one frame is completed.

Next, one embodiment of the operation (output screen configuration) of the screen synthesizing circuit 13 will be described with reference to FIG. As for the size configuration of the input screen, the input screen configuration 14a is 8 blocks × 8 blocks, the input screen configuration 14b is 6 blocks × 6 blocks,
The input screen configuration 14c is composed of 5 blocks × 5 blocks, the input screen configuration 14d is composed of 16 blocks × 16 blocks, and the output screen configuration 15 is composed of 16 blocks × 16 blocks. The same applies to the output video 16. Screen synthesis circuit 1
3 recognizes the number of blocks from each input screen configuration and incorporates them
The screen composition control unit determines the output screen configuration. This screen
The screen configuration can be changed during reception by the configuration control unit,
If the same video encoded data is received at multiple other points
However, the layout of the output screen configuration can be freely adjusted at each reception point.
It can be carried out.

The output screen configuration in the screen synthesizing circuit 13 has an address indicating a position in units of each block or M blocks × N blocks (M and N are natural numbers), and a screen synthesizing control unit incorporating the address. To the screen
Reading from the reception buffers 2a to 2d by the configuration controller
, The video encoded data is arbitrarily synthesized. In this example, since the total number of input blocks is larger than the number of output blocks, the input encoded data in the overlapped portion is discarded. Then, a combined screen equal to the number of output blocks is generated and transmitted to the variable length decoding circuit 3. An output video 16 shows a synthesis example of the input screen.

[0016]

As described above, according to the present invention, a picture synthesizing circuit is provided between the reception buffer memory and the variable length decoding circuit, and the picture synthesizing circuit allows the picture synthesizing circuit from each of multiple points.
Input video encoded data of arbitrary number of blocks sent
Are sent from multiple points when combining before decoding
The sum of the number of blocks of each video encoded data is the block of the output video.
Delete excess block data if more than locks
If there are few, insert dummy block data,
Match the number of blocks on the composite screen with the number of blocks on the output screen.
Video encoded data from multiple locations
Generate composite screen even if the number of blocks differs depending on the number of blocks
It is possible to combine and display the video coded data from multiple points on one screen with smaller hardware and less processing capacity than the conventional device, and from the receiving side. There is an effect that the number of blocks can be freely selected on the transmission side without a request to the transmission side, and a free screen configuration can be realized on the receiving terminal.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an operation example of the screen composition circuit of the present invention.

FIG. 3 is a block diagram of a conventional video signal multiplex decoding apparatus.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 coded data receiving circuit 2 reception buffer memory 3 variable length decoding circuit 4 adder 5 frame memory 7 D / A conversion circuit 13 screen composition circuit 14 input screen configuration 15 output screen configuration 16 output screen

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-276989 (JP, A) JP-A-63-276938 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 7/32 H04N 7/14

Claims (1)

(57) [Claims] 1. A plurality of coded data receiving circuits for receiving coded video data from a plurality of points, a plurality of reception buffer memories for temporarily storing received coded video data, and a variable length coding A variable-length decoding circuit that converts the reproduced data into inter-frame difference data, and an addition circuit that reproduces the current frame video data by adding the reproduced previous frame video data and the received inter-frame difference data. A frame memory for storing the reproduced video data, and a means for converting the reproduced video data into an analog signal and outputting the analog signal, and using the frame darkness correlation of the video signal to reduce the redundancy of the video signal Te in the video signal multiplexing decoder for reproducing original video from the encoded data, any sent from each of a plurality of points
When combining video encoded data for one screen from video encoded data for the number of blocks before decoding ,
The sum of the number of blocks of
Extra block data if more than the number of image blocks
And insert dummy block data if less
The number of blocks on the composite screen and the number of blocks on the output screen.
A video signal multiplex decoding device comprising an image synthesizing circuit for matching .