JPH05328298A - Video recording device - Google Patents

Abstract

PURPOSE:To attain the video recording suitable for the mode of video recording action, especially its recording speed by providing a means to recognize a time interval of each recording relating to sequential recording and a means to select automatically in response to the time interval of the recognized recording to the device. CONSTITUTION:In the case of single shot still picture recording or low speed consecutive shot recording, a line interpolation circuit 3 is used to generate block data and they are compressed to keep high image quality, and in the case of high speed consecutive shot in which the recording speed has priority, no interpolation is conducted and block data are generated and they are compressed by halving number of blocks, and at the time of reproduction, reproduction processing is conducted in matching with recording data to attain video recording at a recording speed suitable for the mode of the video recording action. A selector 4 selects image data fed to either of a terminal 4A and 4B by a select signal fed from a CPU 8 and outputs the data to a DCT transformation section 5. The select signal is outputted based on a signal shot/consecutive shot changeover switch 10A.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video recording device, and more particularly to a video recording device capable of video recording suitable for a recording speed. 2. Description of the Related Art For example, in a video recording apparatus such as an electronic still camera, a video signal to be recorded is subjected to orthogonal transformation and encoding processing to obtain compressed image data, and a memory card or the like is obtained. It is recorded in the data bank. FIG. 8 shows a configuration example of a conventional video signal recording apparatus. During recording, the input video signal is
A memory unit 2A which is converted into a digital signal by the A / D converter 1 and includes a frame memory or a field memory
Recorded in. Writing of data to the memory unit 2A is performed by raster writing as shown in FIG. In FIG. 9, a video signal is obtained as a pixel-corresponding signal of, for example, an image pickup device (for example, CCD), and an effective screen corresponds to 768 pixels in the horizontal direction and 480 pixels in the vertical direction in FIG. In the writing to the memory unit 2A, the pixel corresponding signal in the 1st horizontal direction is written in the 0th line in the vertical direction, the pixel corresponding signal in the 1st line in the vertical direction is written, and thereafter, writing is similarly performed. The data written in the memory unit 2A in this way is
As shown in FIG. 10, the block is read out and sent to the DCT conversion section 5 as block data. In FIG.
Block data is set to data corresponding to 8 × 8 pixels, and block data # 1, # 2, # 3, # 4, ...
After the block data in the horizontal direction is read, the block data # 5 located below the left end block data # 1 is read, the next block data is read in the horizontal direction, and thereafter the same block is read. The block data read from the memory unit 2A is processed by the DCT conversion unit 5
DCT (Discrete Cosine Transform) processing is performed, and encoding processing such as Huffman encoding is performed in the encoding unit 6 to compress the data. The compressed data thus obtained is written in the data bank 7 such as a memory card. The writing and reading control for the memory unit 2A is performed by the memory control unit 9 under the control of the CPU 8 that controls the entire system. At the time of reproduction, the compressed data read from the data bank 7 is decoded by the encoder 6 and output as decompressed data. The decompressed data is subjected to IDCT (Inverse Discrete Cosine Transform) processing by the DCT conversion unit 5, and is written in the memory unit 2A as block data. The image data read from the memory unit 2A in the raster read mode is converted into an analog signal by the D / A converter 13,
For example, it is output as a video signal to the monitor side. When the data stored in the memory unit 2A is field data, it is necessary to obtain frame data by line interpolation processing during reproduction. Therefore, conventionally, as shown in FIG. 11, line interpolation processing is performed and the result is output on the monitor. In FIG. 11, the solid line indicates the odd field data, and the dotted line indicates the even field data. By the way, when compressing image data,
Since compression is performed for each block as shown in FIG. 10, an error occurs with respect to the original image inside the block, so that there is a problem that the image quality of the reproduced image deteriorates when the compressed data is expanded and reproduced. .. In particular, when the subject image is a fine picture, the data amount is limited for each block, and this problem becomes remarkable. Therefore, when the line interpolation process as shown in FIG. 11 is performed and reproduced, one block is composed of 8 lines, and the error is affected over 16 lines in the vertical direction, which is twice that of the block. Deterioration of the image quality over time appears. Therefore, the same applicant as the present application forms a block by line interpolating field data to generate frame data at the time of block transfer (before compression), as shown in FIG. We have proposed a technology that suppresses the occurrence of errors within the line range (Japanese Patent Application No. 3-296441).
No.). FIG. 13 shows a recording sequence of a still image in the video recording device as described above. For example, in the case of an electronic still camera, data is read from the frame memory after exposure of the CCD and writing to the frame memory for one field period. This read processing requires a processing time of two fields because the data is doubled by the line interpolation processing for non-interlacing. The same applies to writing compressed data into a data bank. Then, the microcomputer in the CPU 8 in FIG. 8 also writes the header information (such as discrimination between frame or field data) regarding the compressed data prior to the above writing. Recording of still image data by the video recording apparatus shown in FIG. 13 requires two field times for reading the frame memory and writing compressed data, which is a major factor in determining the recording speed. It becomes a factor, and especially determines the recording speed of continuous shooting for continuous recording at high speed. For example, assuming that the time required for one frame recording sequence is A in FIG. 13, at least N × A time is required for continuous shooting of N frames, which is an obstacle to increasing the recording speed. Therefore, an object of the present invention is to provide a video recording apparatus capable of video recording suitable for the mode of video recording operation, particularly the recording speed. In order to solve the above-mentioned problems, the video recording apparatus according to the present invention provides a video signal sequentially generated by a photographing operation or sequentially supplied from the outside into one image each. A video recording device for performing information compression processing on each corresponding portion and successively recording the information, the first means for recognizing a time interval of each recording relating to the sequential recording, and the information compression processing as a source. The image information is subjected to non-interlace frame processing by the compression processing of the first mode for performing compression, or the original image information is subjected to the compression processing of the second aspect for performing compression on the interlaced field image as it is. Or a second means for automatically selecting whether or not according to the recording time interval recognized by the first means. In the present invention, in the case of single-shot still image recording or low-speed continuous shooting recording, block data is created by line interpolation and then compressed to maintain high image quality. In the case of high-speed continuous shooting in which the recording speed is prioritized, block data is created without interpolation and the number of blocks is halved for compression, and reproduction processing is performed according to the recording data during reproduction. This enables video recording at a recording speed suitable for the mode of video recording operation. Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a video recording apparatus according to the present invention. The embodiment according to the present invention is applied to an apparatus that treats image data as m × n block data, compresses and records the data, and performs decompression processing at the time of reproduction, and records a single still image or low-speed continuous recording. At times, high image quality is maintained by creating block data by line interpolation and then performing compression. On the other hand, at the time of high-speed continuous shooting where the recording speed is prioritized, block data is created without performing interpolation and the number of blocks is halved for compression, and at the time of reproduction, the attribute of the recorded data is determined and matched with the recorded data. Perform playback processing. At the time of recording, the input video signal is converted into a digital signal by the A / D converter 1 and raster-recorded in the frame memory 2. At the time of single shooting or low-speed continuous shooting, the data read in block units from the frame memory 2 is sent to the line interpolation unit 3 and subjected to line interpolation processing,
It is supplied to the terminal 4B of the selector 4. Selector 4 is C
According to the select signal supplied from the PU 8, the image data supplied to either the terminal 4A or 4B is selected and output to the DCT conversion unit 5. The select signal is
Sequential shooting / single shooting switch 10A provided on the operation unit 10
It is output from the CPU 8 based on the operation information. DCT
The transform coefficient data obtained by the transform unit 5 is coded by the coding unit 6 and written in the data bank 7 as compressed data. On the other hand, when a high-speed continuous shooting operation is instructed by the continuous shooting / single shooting switch 10A, the selector 4 responds to a select signal from the CPU 8 to line-up the image data read from the frame memory 2 supplied to the terminal 4A. It is directly supplied to the DCT conversion unit 5 without being interpolated. After that, the compressed data is written in the data bank 7 as field data through the DCT process and the encoding process as in the single-shot operation. At the time of reproducing the recorded data of the single shot or the low speed continuous shot, the data read from the data bank 7 is decoded by the encoder 6 and subjected to IDCT processing by the DCT converter 5,
It is written in the frame memory 2. The image data read in raster form from the frame memory 2 is stored in the selector 1
It is converted into an analog signal by the D / A converter 13 via the second terminal 12B and output to the monitor side. Similarly to the selector 4, the selector 12 selectively outputs the data supplied to the terminal 12A or 12B according to the select signal from the CPU 8. That is, when the data read from the frame memory 2 is frame data, the terminal 12B
Data to be supplied to the terminal 12 in the case of field data
The data supplied to A is selected and output to the D / A converter 13. Since the data read from the frame memory 2 is the field data when the recorded data of the high-speed continuous shooting is reproduced, the pseudo frame circuit 11 creates the frame data using the read field data. Output to the D / A converter 13 via the terminal 12A of the selector 12. By reading the header information of the image data recorded in the data bank 7, the CPU 8 can determine whether the image data is field data or frame data. In the case of a single-shot operation or the like in which the recording speed is not high as described above, high-quality video reproduction can be ensured by performing normal line interpolation processing, then performing data compression processing and recording in a data bank. On the other hand, when high-speed recording is required for continuous recording, high-speed performance is prioritized even if the image quality is slightly sacrificed. Therefore, data compression is performed directly by compressing data without performing line interpolation processing. To record. The operation unit 10 is not limited to single shooting and continuous shooting as described above, but a field / frame changeover switch for instructing recording of frame data when the image quality is prioritized and recording of field data when the recording speed is prioritized. 10B can also be provided. FIG. 2 shows the high-speed continuous recording sequence. Data of one field is written in the frame memory, and in order to speed up reading from the frame memory, line interpolation is not performed and field data is read as it is and compressed data is written. The microcomputer additionally records data such as header information. According to the recording sequence as shown in FIG. 2, the 1-field recording sequence is shortened by 1 field as compared with the recording sequence shown in FIG. 13, so that high-speed recording becomes possible. At this time,
As described above, the deterioration of the image quality due to the error at the time of compression is 16
Although it extends over the line, since it is high-speed continuous shooting, the reproduced image is in a state close to a moving image, so there is practically no problem. FIG. 3 shows a configuration example of the pseudo frame circuit 11 in FIG. The input data is supplied to the 1H line memory 111 and one input terminal of the adder 112. The other input terminal of the adder 112 has a 1H line memory 1
The data delayed by 1H by 11 is input. The output of the adder 112 is multiplied by the coefficient ½ in the ½ multiplier 113 and output as average data to the terminal 114B of the changeover switch 114. The changeover switch 114 has a terminal 1
The data from the 1H line memory 111 supplied from 14A and the average data supplied from the terminal 114B are
Selectively output for each field. FIG. 4 shows a configuration example of the line interpolation circuit 3 and the selector 4 of FIG. 1 for 8 × 8 block data. Input data is 8-bit shift register 31
Is supplied to one input terminal of the adder 32. Adder 32
Adds the output of the 8-bit shift register 31 and the input data. The output of the adder 32 is multiplied by the coefficient 1/2 in the 1/2 multiplier 33 and output to the terminal 4B of the selector 4 as average data. The selector 4 switches between the average data from the terminal 4B and the input data from the terminal 4A for every 8 pixels and outputs. FIG. 5 shows a structural example of the frame memory 2 of FIG. The frame memory 2 is composed of two field memories 21 and 22, and reads out and outputs data from either field memory in response to a chip select signal. The memory control section 9 is constructed, for example, as shown in FIG. 6, and outputs the memory address from the address counter 91 which is counted up by the clock CLK. Further, the discrimination signal from the mode discrimination unit 93 which receives the signal from the CPU 8 and discriminates the mode is supplied to the write enable control unit 94, the output enable control unit 95 and the chip enable control unit 96, and from each control unit. The memory write enable signal WE, the memory output enable signal OE, and the memory chip enable signal CS are output. Horizontal sync signal HD, vertical sync signal V
The reset circuit 97 which receives the determination signal from the D and mode determination unit 93 resets the address counter 91. FIG. 7 shows the operation timing of the above embodiment. As shown in (A), the line address at the time of reading at the time of high-speed continuous shooting is output in units of 8 pixels and one block of data is read. As shown in (B), the recording line address during single shooting is an address for reading the same data twice each because the interpolation process is performed. Therefore, 8 bits (8C
The data delayed by LK) is as shown in (C). Further, in the single-shot mode, the transfer data to the DCT is obtained as data (D) in which interpolation data is inserted based on the above data (B) and (C). As shown in (E), the memory write line address at the time of reproduction at the time of single shooting is 16
Switching is performed for each pixel, and the frame memory chip select signal is output for every 8 pixels as shown in (F), and is written alternately in the field memories 21 and 22 of FIG. 5 to be interlaced. As described above, according to the video recording apparatus of the present invention, when there is a difference in recording speed such as in single shooting and continuous shooting, priority is given to image quality priority and recording speed priority. Since the execution of the interpolation process is controlled by this, the recording adapted to the mode instruction of the user can be performed and the usability is remarkably improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a video recording device according to the present invention. FIG. 2 is a diagram showing a high-speed recording sequence in an example of the present invention. FIG. 3 is a block diagram showing a configuration example of a pseudo frame unit according to the embodiment of the present invention. FIG. 4 is a block diagram showing a configuration example of a line interpolation unit in the embodiment of the present invention. FIG. 5 is a block diagram showing a configuration example of a frame memory according to an embodiment of the present invention. FIG. 6 is a block diagram showing a configuration example of a memory control unit according to an embodiment of the present invention. FIG. 7 is a timing chart for explaining the operation in the embodiment of the present invention. FIG. 8 is a configuration block diagram of a conventional video recording device. FIG. 9 is a diagram for explaining raster writing and reading in a conventional video recording device. FIG. 10 is a diagram for explaining block reading and writing in a conventional video recording device. FIG. 11 is a diagram showing a form of line interpolation data in a conventional video recording device. FIG. 12 is a diagram showing a form of line interpolation data in a conventional video recording device. FIG. 13 is a diagram showing a general still image recording sequence. [Explanation of Codes] 1 A / D converter 2 Frame memory 2A Memory unit 3 Line interpolation circuit 4, 12 Selector 5 DCT
Conversion unit 6 Encoding unit 7 Data bank 8 CPU 9 Memory control unit 10 Operation unit 10A Continuous shooting /
Single shooting switch 10B Field / frame switch 11 Pseudo frame circuit 13 D / A
converter

Claims (1)

What is claimed is: 1. A video recording apparatus, wherein video signals sequentially generated by a photographing operation or sequentially supplied from the outside are subjected to information compression processing for each portion corresponding to one image and continuously and sequentially recorded. The first time interval for recognizing the time interval of each record related to the above-mentioned sequential record.
And the above information compression processing is performed by the compression processing of the first mode in which the original image information is subjected to non-interlaced frame processing and the original image information is compressed as it is in the interlaced field image. A second means for automatically selecting whether to perform the compression processing of the second aspect to be performed according to the recording time interval recognized by the first means. Video recording device.