JP4250229B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus, and more particularly to interpolation of an image signal.
[0002]
[Prior art]
Conventionally, various methods as described below have been proposed as techniques for obtaining a still image.
[0003]
First, a method of obtaining a still image by writing an image signal for one frame in a memory and reading the image signal for one frame as it is can be considered. However, this method requires a memory for one frame, and an image is blurred when there is a motion between two fields constituting one frame.
[0004]
On the other hand, the image signal for one field is written in the memory, the image signal stored in the memory is used as it is for one field, and the image signal of the upper line or the lower line is used as it is for the other field. A method for obtaining a still image of one frame by interpolation is known.
[0005]
According to this method, the capacity of the memory is only one field, and image blur due to movement between fields does not occur. However, although it looks like an image of one frame, in reality, since two consecutive lines are the same image signal, the resolution in the vertical direction is lower than that in the above method using the frame memory.
[0006]
For this reason, the image signal for one frame is written in the memory, for example, the image signal is output as it is for the first field, and the movement between the pixel and the upper and lower lines is detected for the second field. A method of switching and outputting the image signal itself of the second field or the synthesized image signal according to the movement is considered.
[0007]
That is, when there is no motion, the image signal of the second field is read out from the memory as it is and output, and when there is motion, the image signal of the second field is interpolated by the image signal of the first field of pixels that are close to each other vertically Output.
[0008]
According to this method, it is possible to prevent a reduction in vertical resolution and image blur due to movement between fields.
[0009]
[Problems to be solved by the invention]
However, as described above, when the second field image and the interpolated image are switched and output according to the motion, an image signal of three pixels continuous in the vertical direction is required for motion detection.
[0010]
For this purpose, a memory accessible at three times the normal speed is required, but a high-speed memory is expensive.
[0011]
Although it is possible to detect motion without using such a high-speed memory, this requires a memory for at least two lines, which increases the circuit scale.
[0012]
The object of the present invention is to solve the above-mentioned problems.
[0013]
Still another object of the present invention is to obtain a high-definition interpolated image without increasing the circuit scale.
[0014]
[Means for Solving the Problems]
Under such a purpose, in the present invention, one frame is composed of a first field and a second field interlaced with each other, and m pixels in the vertical direction × n pixels in the horizontal direction (m and n are each 2 or more). Input means for inputting an image signal encoded in units of blocks composed of integers), decoding means for decoding the image signals input by the input means and outputting them in units of blocks, and the decoding means Based on the memory for delaying the output image signal for a period corresponding to n pixels, the image signal output from the decoding means, and the image signal delayed by the memory, the image signal of the first field in the block And a motion detection means for detecting a motion between the image signal of the second field, an image signal output from the decoding means, and the memory By calculating the extended image signal according to the detection result of the motion detection means, an interpolated image signal in which the image signal of the first field and the image signal of the second field in the block are synthesized is generated. Interpolating means for outputting the first field image signal output from the decoding means as the first field image signal in the block and outputting the interpolated image signal as the second field image signal in the block With.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a block diagram showing the configuration of a VTR playback system to which the present invention is applied.
[0017]
The VTR according to the present embodiment reproduces an image signal whose information amount is compressed using well-known block coding such as DCT and variable length coding at the time of recording.
[0018]
In the figure, a reproduction circuit 103 reproduces an image signal compressed and encoded as described above from a tape 101, and performs a known process such as an error correction process using an error correction code added at the time of recording. To 105.
[0019]
The variable length code decoding circuit 105 performs a variable length code decoding process corresponding to the recording time on the image signal from the reproduction circuit 103 and outputs the decoded signal to the inverse quantization circuit 107. The inverse quantization circuit 107 inversely quantizes the reproduction signal according to the quantization coefficient corresponding to the recording time, and outputs it to the inverse DCT circuit 109. The image signal in this embodiment is subjected to DCT processing for every 8 vertical pixels × 8 horizontal pixels during recording, and the inverse DCT circuit 109 performs inverse DCT processing on the image signal output from the inverse quantization circuit 107. And convert the DCT coefficient into normal image data.
[0020]
The image signal output in units of blocks from the inverse DCT circuit 109 is written in the memory 113 via a still image processing circuit 111 described later. Then, the data is read from the memory 113 in the order of raster scan, and output to an external monitor or the like by the output circuit 115.
[0021]
Now, in such a configuration, an operation when an instruction to reproduce a still image is given by the operation unit 119 will be described.
[0022]
When there is an instruction to reproduce a still image from the operation unit 119, the control circuit 117 outputs a control signal for temporarily stopping the conveyance of the tape 101 to the reproduction circuit 103 and outputs a still image to the still image processing circuit 111. A control signal for performing processing is output.
[0023]
FIG. 2 is a diagram illustrating a configuration of the still image processing circuit 111.
[0024]
Image signals that have been subjected to inverse DCT processing by the inverse DCT circuit 109 are output in block units in the order shown in FIG. 3, and are output to the 8-pixel memory 201, the motion amount detection circuit 207, and the interpolation signal generation circuit 205. . The 8-pixel memory 201 delays the input image signal for a period corresponding to 8 pixels and outputs it to the interpolation signal generation circuit 205, the motion amount detection circuit 207, and the 8-pixel memory 203. The 8-pixel memory 203 further delays the image signal from the 8-pixel memory 201 for a period corresponding to 8 pixels and outputs it to the interpolation signal generation circuit 205 and the motion amount detection circuit 207.
[0025]
As described above, the image signal of three pixels continuous in the vertical direction within one block is output to the interpolation signal generation circuit 205 and the motion amount memory 209. As shown in FIG. 4, the motion amount detection circuit 207 averages the value of the image signal of the center pixel C and the values of the image signals of the pixels A and B above and below the image signal of the continuous three pixels. A difference β from the value AVE is obtained, and this β is output as a motion amount to the interpolation signal generation circuit 205 and the motion amount memory 209. The motion amount detection circuit 207 also outputs the difference TH between the pixels A and B to the interpolation signal generation circuit 205 at that time.
[0026]
Here, as shown in FIG. 3, the image signal of each block is composed of odd line image signals indicated by 1o, 2o, 3o, and 4o and even line image signals indicated by 1e, 2e, 3e, and 4e. Has been. In this embodiment, the odd-field image signal is output to the memory 113 as it is, and the even-field image signal is generated by the interpolation signal generation circuit 205 based on the output of the motion amount detection circuit 207 and the memory 113. Output to.
[0027]
Based on the motion amount β output from the motion amount detection circuit 207 and the difference TH between the values of the image signals of the pixels A and B, the interpolation signal generation circuit 205 performs an image signal of the pixel C, the pixel A, and The interpolated signal is generated by combining the average value AVE of B.
[0028]
Interpolated signal c = (1-α) C + αAVE
[0029]
Here, α is a coefficient for determining the ratio of synthesis of the pixel C and AVE. Specifically, the interpolated image generation circuit 205 changes the value of α between 1.0 and 0.0 while the value of β changes from 0 to TH as shown in FIG.
[0030]
FIG. 6 shows how the pixel C and AVE are combined at this time.
[0031]
As shown in FIG. 6, when the motion amount β is 0, the image signal of the pixel C is output as it is as an interpolated image signal, and the proportion of AVE increases as the motion amount β increases, and β becomes greater than TH. In this case, AVE is output as it is.
[0032]
If the interpolated pixels are the upper and lower end portions of the block, for example, the line 4e in FIG. In step S209, the interpolation signal generation circuit 205 generates an interpolation image signal using the motion amount β of the previous frame.
[0033]
Similarly, when the image signal of 3 pixels in the same block used for generating the interpolated image signal cannot be obtained because of the block end, that is, the pixel of the line 4e in FIG. An interpolation image is generated using, for example, one line of pixels to be interpolated, that is, the pixels of the line 4o, stored in 203.
[0034]
That is, when the image signal of the line 4e is interpolated, an interpolated image signal is obtained by changing the synthesis ratio of the pixel of the line 4e and the pixel of the line 4o according to the motion.
[0035]
As described above, in this embodiment, when a still image is obtained by interpolating an image signal according to motion, interpolation processing is performed in a state of being output in blocks from the inverse DCT circuit. Therefore, it is only necessary to provide two 8-pixel memories, and a line memory becomes unnecessary.
[0036]
Therefore, a high-definition still image (interpolated image) can be obtained without increasing the circuit scale.
[0037]
In this embodiment, as shown in FIG. 5, the value of α is continuously changed to generate an interpolated image. However, in order to simplify the circuit, α is changed stepwise, as shown in FIG. An interpolated image signal may be generated.
[0038]
Further, in this embodiment, the block size is 8 pixels × 8 pixels, but other sizes may be used. For example, assuming that the size of a block is vertical m pixels × horizontal n pixels, when outputting the image signal of each block as shown in FIG. Can be generated.
[0039]
In the above-described embodiment, the motion is detected based on the average value AVE of the pixel C, the pixels A, and B. However, the present invention is not limited to this. For example, the motion is detected based on the difference between the pixel C and the pixel A. Alternatively, the motion may be detected based on the difference between the pixel C and the pixel B. In this case, it is sufficient to provide only one 8-pixel line memory, and the circuit scale can be further reduced as compared with that in FIG.
[0040]
Next, another embodiment of the present application will be described.
[0041]
FIG. 8 is a block diagram showing a configuration of a recording system of a VTR to which the present invention is applied. The same components as those in FIG. 1 will be described with the same numbers.
[0042]
In the figure, an imaging circuit 301 captures a subject image, converts it into an image signal, and writes it into the memory 303. The still image processing circuit 111 reads out the image signal written in the memory 303 in units of 8 pixels × 8 pixels in the order shown in FIG. 3 and outputs it to the DCT circuit 305.
[0043]
The DCT circuit 305 performs DCT processing on the image signal read in block units, converts the image signal into DCT coefficients, and outputs the DCT coefficient to the quantization circuit 307. The image signal output from the DCT circuit 305 is quantized by a quantization circuit 307 with a quantization coefficient determined so as to have a constant code amount for each predetermined number of blocks, and further in a variable length coding circuit 309. It is encoded and output to the recording circuit 311. The recording circuit 311 subjects the image signal encoded by the variable length encoding circuit 309 to processing such as synchronization signal disabling, error correction encoding, and digital modulation, and records the result on the tape 101.
[0044]
In the configuration of FIG. 7, when the operation unit 119 instructs to record a still image, the control circuit 117 outputs a control signal to the memory 303 to prohibit writing of an image signal and A control signal indicating that is output to the image processing circuit 111.
[0045]
The still image processing circuit 111 has the same configuration as that shown in FIG. 2, and detects the movement of the image signal output from the memory 303 in units of blocks in the same manner as the embodiment pair in FIG. An interpolated image signal is generated.
[0046]
The still image signal generated by the still image generation circuit 111 is output to the DCT circuit 305 in units of blocks in the same way as in normal recording, and is compressed and recorded.
[0047]
As described above, also in this embodiment, when a still image is obtained by interpolating an image signal in accordance with the motion, the interpolation processing is performed in a state of being output in blocks from the inverse DCT circuit. Therefore, it is only necessary to provide two 8-pixel memories, and a line memory becomes unnecessary.
[0048]
In particular, when an interlace readout type CCD is used as an image sensor, a remarkable effect can be obtained as compared with the conventional system.
[0049]
In the above-described embodiment, the case where the present invention is applied to a VTR has been described. However, the present invention is not limited to this, and the present invention can be applied when interpolating an image signal processed in units of blocks. It has the effect of.
[0050]
The motion detection processing by the motion amount detection circuit 207 and the interpolation signal generation processing by the interpolation signal generation circuit 205 shown in FIG. 2 can be executed by software processing using a microcomputer. It has the same effect as the embodiment.
[0051]
In addition, a computer-readable storage medium that stores each step of the program at this time is also a configuration of the present invention.
[0052]
【The invention's effect】
As described above, according to the present invention, when one field image signal is interpolated using the other field image signal, a high-definition interpolated image can be obtained without increasing the circuit scale. .
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a playback system of a VTR to which the present invention is applied.
FIG. 2 is a diagram illustrating a configuration of a still image processing circuit of FIG.
FIG. 3 is a diagram showing a state of an image signal handled by the circuit of FIG. 2;
4 is a diagram for explaining a motion detection operation of the circuit of FIG. 2; FIG.
FIG. 5 is a diagram for explaining the operation of the circuit of FIG. 2;
6 is a diagram for explaining the operation of the circuit of FIG. 2;
7 is a diagram for explaining the operation of the circuit of FIG. 2;
FIG. 8 is a diagram showing a configuration of a recording system of a VTR to which the present invention is applied.

Claims (2)

One frame is composed of the first field and the second field interlaced with each other, and encoding is performed in units of blocks composed of m pixels in the vertical direction and n pixels in the horizontal direction (m and n are each an integer of 2 or more). Input means for inputting the processed image signal;
Decoding means for decoding the image signal input by the input means and outputting the block unit;
A memory that delays the image signal output from the decoding means for a period corresponding to n pixels;
Motion detection for detecting a motion between the image signal of the first field and the image signal of the second field in the block based on the image signal output from the decoding means and the image signal delayed by the memory Means,
By calculating the image signal output from the decoding means and the image signal delayed by the memory according to the detection result of the motion detection means, the image signal of the first field and the second field of the block are calculated. An interpolated image signal synthesized with the image signal is generated, the first field image signal output from the decoding means is output as the first field image signal in the block, and the second field in the block Interpolating means for outputting the interpolated image signal as an image signal.   2. The image processing apparatus according to claim 1, wherein the interpolation unit determines a ratio of the image signal of the first field and the image signal of the second field according to the detection result of the motion detection unit.

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