JP3312456B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for processing a reproduced image signal.

[0002]

2. Description of the Related Art Conventionally, when an image signal captured and recorded by a video camera or the like is reproduced at a speed different from that at the time of recording, when the reproduction speed is low, image data is displayed by overlapping image data. I do. When the reproduction speed is high, only a part of image data in one frame or one field is taken out to display an image, and other image data is discarded. Specifically, for example, when the reproduction speed is n times speed, only 1 / n of image data in one frame or one field is reproduced. In general, a reproduced image signal is processed using such a method to display image data.

[0003]

By the way, when the reproduction speed of the reproduced image data is high, not all the image data is reproduced as described above. In some cases, and it was difficult to obtain an image of an instant scene.

For example, when an object moving at a high speed or a phenomenon that changes instantaneously is recorded only in about 1 to 2 frames, if the recorded image signal is reproduced by thinning it to 1 / n, May not be able to find moving objects or instantly changing phenomena.

In view of the above circumstances, the present invention provides a video signal processing apparatus capable of displaying all image signals reproduced at a high speed.

[0006]

A video signal processing apparatus according to the present invention converts an image of n frames or n fields continuous of an image signal reproduced at n times speed into at least n-1 frames or n-1 fields. Conversion means for converting the image into parallel n-frame or n-field images using the image signal storage means, and n obtained in parallel by the conversion means
The above-mentioned problem is solved by providing image signal output means for adding and averaging an image of a frame or n fields and outputting it as an image signal of one frame or one field.

[0007] The conversion means uses n-1 frame memories or field memories connected in series as the image storage means, and converts n image signals from input / output terminals of each memory in parallel. It is characterized by taking out.

[0008] The video signal processing apparatus according to the present invention comprises:
In a video signal processing apparatus for processing an image signal reproduced at n times speed and supplying the processed image signal to an image display device, an image of continuous n frames or n fields of the image signal reproduced at n times speed is converted into at least n frames or more or A conversion means for converting into a parallel image of n + 1 frames or more or n + 1 fields or more using fields or more, and averaging the parallel images of n + 1 frames or more or n + 1 fields or more obtained in parallel by the conversion means. The above-mentioned problem is solved by having an image signal output means for outputting as one frame or one field image signal.

[0009]

According to the present invention, all image signals reproduced at n times speed are stored in the image signal storage means and taken out in parallel to reproduce all images.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of an image editing system using a video signal processing device according to the present invention.

An image photographed by an imaging device such as a video camera 1 is converted into a signal of a predetermined recording format and recorded on a recording medium such as a cassette tape 2. The image signals recorded on the cassette tape 2 are reproduced by a plurality of reproducers 3 at a high reproduction speed. The reproduced image signal is transferred to the video signal processing device 4 and the editing device 6 according to the present invention. The image signal transferred to the video signal processing device 4 is decoded and converted to a standard speed,
Further, the image signal is converted into an image signal suitable for a display device such as the monitor 5. The converted image signal is sent to the monitor 5 to display an image. Further, the image signal transferred to the editing device 6 is stored in an image editing memory in the editing device 6. Further, during the transfer of the image signal to the editing device 6, the image signal of the image required for editing is detected and marked, thereby improving the efficiency of image editing.

Next, FIG. 2 shows a schematic configuration of a video signal processing apparatus according to the present invention. In the embodiment shown in FIG. 2, a compression encoding process is performed at the time of recording an image signal,
It is assumed that a decoding process for decompressing the image signal is performed when the image signal is reproduced.

An image signal reproduced at a high reproduction speed is input from an image reproduction signal input terminal 10 of the video signal processing apparatus according to the present invention shown in FIG. The image signal reproduced at a high speed may be transmitted as a dubbing signal to a recording device (not shown) as it is, if necessary, to perform so-called high-speed dubbing.

When the input image signal is compression-encoded at the time of recording as described above, the image signal is decoded by the compression decoder 11 so as to decompress the image signal, and sent to the memory circuit 12. Here, the memory circuit 12 includes a frame memory described later,
The number of the frame memories is n-1 or more. For example, if a reproduced image signal of n times speed is sent to the memory circuit 12, the image signal of each frame of the reproduced image signal is written to and read from the frame memory, and reproduced at n times speed. All the image signals from the first frame to the n-th frame are simultaneously processed at least once in the n-frame period of the image signal, that is, at the frame period in the standard reproduction.
Sent to 3.

The n-times reproduced image signal sent to the frame arithmetic unit 13 is added and averaged, and then converted into an image signal necessary for display on a display device such as a monitor 5 shown in FIG. 14 is input. In the image output interface unit 14, the input image signal is converted into an image signal that can be displayed on a display device at the output destination, and output from the image signal output terminal 15.

Next, the memory circuit 12, the frame operation unit 13, and the image output interface unit 14 shown in FIG.
FIG. 3 shows an example of the detailed configuration of FIG. Specifically, a configuration in a case where an image signal reproduced at 4 × speed is input is shown. FIG. 4 shows the timing of each signal in the configuration of FIG.

The reproduced quadruple-speed image signal shown in FIG. 4C is input from a quadruple-speed image signal input terminal 20. More specifically, since the four-times image signal is reproduced at a standard reproduction speed while the image signal for one frame is reproduced, the image signal for one frame at the standard speed is reproduced. An image signal for four frames is input in the signal input time.

The first of the input quadruple-speed image signals is
The image signal of the frame is transmitted to the frame memories 21, 22, 2
3 is delayed by three frames, and
4 The image signal of the second frame of the quadruple speed image signal is delayed by two frames via the frame memories 21 and 22 and sent to the adder 24. Further, the image signal of the third frame of the quadruple-speed image signal is delayed by one frame via the frame memory 21 and sent to the adder 24. Further, the image signal of the fourth frame of the quadruple-speed image signal is not delayed since it does not pass through the frame memory. As described above, the image signal of the first frame, the image signal of the second frame, and the third
The image signals of the frames are respectively delayed, and the image signals of four frames are simultaneously sent to the adder 24 at the input timing of the image signal of the fourth frame to the adder 24.

On the other hand, a frame signal shown in FIG. 4A synchronized with the quadruple-speed image signal is input from the frame signal input terminal 25 and sent to the frequency divider 26. This divider 26
In FIG. 4, the input frame signal is frequency-divided into quarters.
(B) is output. The enable signal is input to the adder 24, and becomes "1" only at the output timing of the image signal of the fourth frame of the quadruple-speed image signal. When the enable signal is “1”, the adder 24 converts the input image signal of the first frame, the image signal of the second frame, the image signal of the third frame, and the image signal of the fourth frame. It is added for each pixel. The frame signal that is the added image signal is output to the divider 27.

The divider 27 divides the input frame signal by a quarter to output an operation output signal shown in FIG. 4D. This calculation output signal is input to the image output interface unit 14. In the image output interface unit 14, the input operation output signal is stored in a memory, decoded, and further subjected to signal processing such as D / A (digital / analog) conversion, thereby adapting to an output destination display device. An image signal for one frame, that is, a buffer output signal shown in FIG. 4e is output to a display device such as the monitor 5 in FIG. 1 when the next quadruple-speed image signal is input from the quadruple-speed image signal input terminal 20. Is done.

Specifically, the output signal from the divider 27 is
The operation output signal E of FIG. ₁Is the next 4x image
The input signal of the image signal from the image reproduction signal input terminal 10
The buffer output signal E of FIG.₁When
And output the next 4x image signal.
Calculated output signal E_TwoAbove the next 4x image signal
The timing of input from the image reproduction signal input terminal 10 and
At the same time, the buffer output signal E of FIG._TwoOutput as
Will be. Such a video signal processing according to the present invention
Image signal reproduced at n times speed by using the device
Display all the image data for n frames in
It is possible to display an image of a natural movement.

When an n-times speed image signal is input to the video signal processing device according to the present invention, the number of the frame memories is set to n or more, and the number of the frame memories is n.
For image signals of a predetermined frame of n + 1 or more frames, image signals of some frames are redundantly written to the n or more frame memories, and image signals are generated by averaging to generate an image signal having a more natural motion. Can be displayed.

When an n-times speed image signal is input to the video signal processing apparatus according to the present invention, one frame for writing and reading is used for one frame in the image signal reproduced at n times speed. In this manner, n pairs of frame memories, one pair each, are prepared by using each frame memory. At this time, the image signals up to the n-th frame of the image signal previously reproduced at the n-times speed are written and stored for each frame in one of the n frame memories in the n pairs, and the stored n is stored. At the time of outputting the image signals for the frames to the adder, the image signals reproduced at the next n times speed are written into the other n frame memories in the n pairs different from the n frame memories for each frame. By switching between the n pairs of frame memories and writing and reading image signals for n frames, the image signals for each frame reproduced at n times speed are converted to image signals for each frame at the standard reproduction speed. It can be converted and played.

The image output interface unit 1
In 4, when the input operation output signal is decoded, an image signal suitable for the display device of the output destination, for example, an NTSC signal or PAL signal for color television, and an RGB signal or C _R / C _B. / Y signals can be converted into various image signals.

Further, in the above embodiment, the case where the quadruple-speed image signal is input has been described in detail. However, when the n-times image signal is input, n is not an integer, that is, has a value below the decimal point. At times, a frame memory is prepared using the rounded-up value of n, and a synchronizer is added in the image output interface unit 14, whereby the same effect as in the above embodiment can be obtained.

In addition, although the description has been given of the compressed image data as the image data input to the video signal processing apparatus according to the present invention, the same applies to the case where the non-compressed image data is used as in the case where the compressed image data is used. The present invention can be applied to the video signal processing device according to the present invention.

Here, in the above embodiment, the case where signal processing is performed in units of frames has been described, but it is also possible to use units of fields instead of units of frames. In this case, field processing of the even field and the odd field is further required.

[0028]

As is clear from the above description, the video signal processing apparatus according to the present invention converts an image of continuous n frames or n fields of an image signal reproduced at n times speed into
A conversion means for converting into an image of n frames or n fields in parallel using image signal storage means of at least n-1 frames or n-1 fields; and n frames or n fields obtained in parallel by the conversion means Image signal output means for averaging and averaging the images and outputting the resulting image signal as one frame or one field image signal. Can be played at high speed. Further, the editing apparatus can check the contents of all the image data at high speed, and can determine the editing block of the image at the same time as the dubbing, thereby shortening the image editing processing time.

Further, the conversion means uses an image storage means in which n-1 frame memories or field memories are connected in series, and converts n image signals from input / output terminals of each memory in parallel. Thus, all the image data can be reproduced at high speed without thinning out the image data of the image signal reproduced at high speed.
Further, the editing apparatus can check the contents of all the image data at high speed, and can determine the editing block of the image at the same time as the dubbing, thereby shortening the image editing processing time.

Further, the conversion means uses the image signal storage means with n frames or more or n fields or more,
The image signals are converted into parallel images of n + 1 frames or more or n + 1 fields or more, and the image signal output means adds and averages the converted parallel images of n + 1 frames or more or n + 1 fields or more to obtain one frame or one field. By outputting as image signals, all image data can be reproduced at high speed without thinning out image data of image signals reproduced at high speed. Further, the editing apparatus can check the contents of all the image data at high speed, and can determine the editing block of the image at the same time as the dubbing, thereby shortening the image editing processing time.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an image editing system using a video signal processing device according to the present invention.

FIG. 2 is a diagram showing a schematic configuration of a video signal processing device according to the present invention.

3 is a memory circuit 12 and a frame operation device 1 shown in FIG.
3 is a diagram illustrating an example of a detailed configuration of an image output interface unit 14; FIG.

FIG. 4 is a diagram showing the timing of each signal in the configuration of FIG. 3;

[Explanation of symbols]

 11: Compression decoder 12: Memory circuit 13: Frame operation unit 14: Image output interface unit 21, 22, 23, Frame Memory 24: Adder 25: Divider 26: Divider 27: Divider

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956

Claims (3)

(57) [Claims] 1. A video signal processing device for processing an image signal reproduced at n times speed and supplying the processed image signal to an image display device, wherein at least n consecutive frames or n fields of the image signal reproduced at n times speed are imaged at least. a conversion means for converting into an image of n frames or n fields in parallel using an image signal storage means of n-1 frames or n-1 fields; and n frames or n obtained in parallel by the conversion means
Image signal output means for adding and averaging field images and outputting as one frame or one field image signal. 2. The conversion means uses n-1 frame memories or field memories connected in series as the image storage means, and converts n image signals from input / output terminals of each memory in parallel. 2. The video signal processing device according to claim 1, wherein the video signal is extracted from the video signal. 3. A video signal processing device for processing an image signal reproduced at n times speed and supplying the processed image signal to an image display device, wherein at least n consecutive frames or n fields of the image signal reproduced at n times speed are imaged at least. a conversion means for converting into a parallel image of n + 1 frames or more or n + 1 fields or more using n frames or more or n fields or more; and a parallel n + 1 frame or more or n + 1 fields or more obtained in parallel by the conversion means. A video signal processing device comprising: image signal output means for averaging and averaging the images and outputting as an image signal of one frame or one field.