JPH07193787A - Video signal processor - Google Patents

Abstract

PURPOSE:To display all-picture signals reproduced at a high speed by storing all picture signals reproduced at n-times speed in a picture signal storing means and extracting the stored signals in parallel. CONSTITUTION:When reproduced picture signals with n-times speed are sent to a memory circuit 12, the picture signals are written/read out in/from a frame memory and all picture signals from a 1st frame to an n-th frame are simultaneously sent to a frame arithmetic unit 13 at least once in a frame period for reference reproducing. An arithmetical mean for the reproduced picture signals with n-times speed which are sent to the unit 13 are calculated and the arithmetical mean value is inputted to a picture output interface part 14 as a picture signal necessary for displaying a picture on a display device such as a monitor. The interface part 14 converts the inputted picture signal into a picture signal to be displayed on the display device to be an output destination and the converted signal is outputted from a picture signal output terminal 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for processing a reproduced image signal.

[0002]

2. Description of the Related Art Conventionally, when an image signal captured and recorded by a video camera or the like is reproduced at a speed different from that at the time of recording, and when the reproduction speed is low, the image data is displayed by overlapping the image data. To do. When the reproduction speed is high, only part of the image data in one frame or one field is taken out to display the image, and the other image data is discarded. Specifically, for example, when the reproduction speed is n times speed, only 1 / nth of image data in one frame or one field is reproduced. It is general to process the reproduced image signal and display the image data by using such a method.

[0003]

By the way, when the reproduction speed of the image data to be reproduced is high, not all the image data is reproduced as described above, and therefore the image is changed by one frame difference. Occasionally, it was difficult to obtain an image of a momentary scene.

For example, when an object that moves at high speed or a phenomenon that changes instantaneously is recorded in only about 1 to 2 frames, if the recorded image signal is thinned out to 1 / n and reproduced, Sometimes you can't find moving objects or phenomena that change instantly.

In view of the above situation, the present invention provides a video signal processing device capable of displaying all image signals reproduced at high speed.

[0006]

SUMMARY OF THE INVENTION A video signal processing apparatus according to the present invention is capable of converting at least n-1 frames or n-1 fields of continuous n frames or n fields of an image signal reproduced at n times speed. Conversion means for converting into parallel n-frame or n-field images using the image signal storage means and n obtained in parallel by the conversion means
The above-mentioned problems can be solved by comprising an image signal output means for adding and averaging images of frames or n fields and outputting as an image signal of one frame or one field.

The converting means uses n-1 frame memories or field memories connected in series as the image storing means, and n image signals from the input / output terminals of each memory are parallelized. It is characterized in that it is taken out.

Further, the conversion means uses the image signal storage means for n frames or more or n fields or more,
The image signals are converted into parallel images of n + 1 frames or more or n + 1 fields or more, and the image signal output means adds and averages the converted images of parallel n + 1 frames or more or n + 1 fields or more to obtain one frame or one field. It is characterized in that it is output as an image signal.

[0009]

In the present invention, all images are reproduced by storing all the image signals reproduced at n-times speed in the image signal storage means and extracting them in parallel.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of an image editing system using a video signal processing device according to the present invention.

An image taken by an image pickup device such as the video camera 1 is converted into a signal of a predetermined recording format and recorded on a recording medium such as a cassette tape 2. The image signal recorded on the cassette tape 2 is reproduced at a high reproduction speed by the plurality of reproducing devices 3. The reproduced image signal is transferred to the video signal processing device 4 and the editing device 6 according to the present invention. The image signal transferred to the video signal processing device 4 is decoded and converted into a standard speed,
Further, it is converted into an image signal suitable for a display device such as the monitor 5. An image is displayed by sending the converted image signal to the monitor 5. The image signal transferred to the editing device 6 is stored in the image editing memory in the editing device 6. Further, while the image signal is being transferred to the editing device 6, the image signal of the image required for editing is detected and marked, so that the efficiency in editing the image can be improved.

Next, FIG. 2 shows a schematic configuration of a video signal processing device according to the present invention. In the embodiment shown in FIG. 2, compression encoding processing is performed at the time of recording an image signal,
It is assumed that a decoding process that removes the above compression is performed at the time of reproducing the image signal.

An image reproduction signal input terminal 10 of the video signal processing apparatus according to the present invention shown in FIG. 2 receives an image signal reproduced at a high reproduction speed. The image signal reproduced at high speed may be transmitted as a dubbing signal to a recording device or the like (not shown) as it is, if necessary, so as to perform so-called high-speed dubbing.

When the input image signal is compression-encoded at the time of recording as described above, the compression decoder 11 performs a decoding process so as to release the compression, and is sent to the memory circuit 12. Here, a frame memory described later is included in the memory circuit 12,
The number of frame memories is n-1 or more. For example, if a reproduced image signal of n times speed is sent to the memory circuit 12, the image signal of each frame of the reproduced image signal is written in and read from the frame memory to be reproduced at n times speed. At least once in the n-frame cycle of the image signal, that is, in the frame cycle at the time of standard reproduction, all the image signals from the first frame to the n-th frame are simultaneously processed by the frame operation device 1
Sent to 3.

The n-fold speed reproduced image signal sent to the frame arithmetic unit 13 is added and averaged, and then an image output interface unit is provided as an image signal necessary for display on the display device such as the monitor 5 shown in FIG. 14 is input. In the image output interface unit 14, the input image signal is converted into an image signal that can be displayed on the output destination display device, and is output from the image signal output terminal 15.

Next, the memory circuit 12, the frame arithmetic unit 13, and the image output interface section 14 shown in FIG.
FIG. 3 shows an example of the detailed configuration of the above. Specifically, the configuration is shown in the case where an image signal reproduced at 4 × speed is input. Further, FIG. 4 shows the timing of each signal in the configuration of FIG.

The reproduced 4 × speed image signal shown in FIG. 4C is inputted from the 4 × speed image signal input terminal 20. Specifically, in the 4 × speed image signal, since the image signal for 4 frames is reproduced while the image signal for 1 frame is reproduced at the standard reproduction speed, the image for 1 frame at the standard speed is reproduced. Image signals for four frames are input at the time when the signals are input.

The first of the input 4 × speed image signals
The image signal of the frame is stored in the frame memories 21, 22, 2
3 is delayed by 3 frames, and the adder 2
Sent to 4. Further, the image signal of the second frame of the quadruple speed image signal is delayed by two frames by passing through the frame memories 21 and 22 and sent to the adder 24. Further, the image signal of the third frame of the quadruple speed image signal is delayed by one frame by passing through the frame memory 21 and sent to the adder 24. Further, the image signal of the fourth frame of the quadruple speed image signal is not delayed because it does not pass through the frame memory. Thus, the image signal of the first frame, the image signal of the second frame, and the third
The image signals of the frames are delayed, and the image signals of four frames are simultaneously sent to the adder 24 at the input timing of the image signals of the fourth frame to the adder 24.

On the other hand, from the frame signal input terminal 25, the frame signal shown in FIG. 4a synchronized with the 4 × speed image signal is input and sent to the frequency divider 26. This divider 26
Then, divide the input frame signal into quarters,
It outputs the enable signal shown in b. This enable signal is input to the adder 24, and becomes "1" only at the output timing of the image signal of the fourth frame of the quadruple speed image signal. When the enable signal is "1", the adder 24 outputs the input first frame image signal, second frame image signal, third frame image signal, and fourth frame image signal. It is added for each pixel. The frame signal which is the added image signal is output to the divider 27.

The divider 27 divides the input frame signal into quarters to output the operation output signal shown in d of FIG. This operation output signal is input to the image output interface unit 14. The image output interface unit 14 is adapted to the display device of the output destination by storing the input operation output signal in the memory, decoding it, and further performing signal processing such as D / A (digital / analog) conversion. The image signal for one frame, that is, the buffer output signal shown in e of FIG. 4 is output to the display device such as the monitor 5 of FIG. 1 when the next 4 × image signal is input from the 4 × image signal input terminal 20. To be done.

Specifically, the output signal from the divider 27 is
Output signal E of FIG. ₁Is the next 4x speed image
Input of the image signal from the image reproduction signal input terminal 10
Simultaneously with the imming, the buffer output signal E of FIG.₁When
Output, and the next quadruple speed image signal is converted.
Calculated output signal E₂On the next 4x image signal
Input timing from the image reproduction signal input terminal 10
At the same time, the buffer output signal E of FIG.₂Output as
Will be done. Such video signal processing according to the present invention
Image signal reproduced at n times speed by using the device
Since all the image data for n frames in the
It is possible to display an image of natural movement.

When an nx speed image signal is input to the video signal processing device according to the present invention, the number of frame memories is n or more, and n frame cycles for nx speed reproduction,
Regarding image signals of a predetermined frame of n + 1 frames or more, image signals of some frames are overlapped and written in the n or more frame memories, and arithmetic mean is generated to generate an image signal of a more natural motion. Can be displayed.

When an n-fold speed image signal is input to the video signal processing device according to the present invention, one frame is written for each frame in the image signal reproduced at n-times speed, and one frame is used for reading. Each frame memory is used to prepare n pairs of frame memories, one pair for each. At this time, the image signals up to the n-th frame of the image signal previously reproduced at the n-fold speed are written and stored for each frame in the n frame memories in each of the n pairs, and the stored n signals are stored. At the time of outputting the image signal for the frame to the adder, the image signal reproduced at the next n times speed is written for each frame in the other n frame memories in each n pair different from the above n frame memories. The image signal for each frame reproduced at n times speed is converted into the image signal for each frame at the standard reproduction speed by storing and storing the image signals for n frames by switching the n pairs of frame memories. It can be converted and played.

The image output interface section 1 is also provided.
4, when the input operation output signal is decoded, an image signal adapted to the display device at the output destination, for example, an NTSC signal or PAL signal for color television, and an RGB signal or C _R / C _B It is possible to convert into various image signals such as / Y signal.

Further, in the above embodiment, the case where the 4 × speed image signal is input has been described in detail, but when the n × speed image signal is input, n is not an integer, that is, has a value below the decimal point. At times, a frame memory is prepared by using the rounded-up value of n, and a synchronizer is added in the image output interface unit 14 to obtain the same effect as that of the above embodiment.

Moreover, although the compressed image data has been described as the image data input to the video signal processing device according to the present invention, even when the uncompressed image data is used, the same as when the compressed image data is used. The present invention can be applied to the video signal processing device according to the present invention.

In the above embodiment, the case where the signal processing is performed in frame units has been described, but it is also possible to use field units instead of frame units. In this case, field processing of even field and odd field is further required.

[0028]

As is apparent from the above description, the video signal processing device according to the present invention can generate an image of consecutive n frames or n fields of an image signal reproduced at n times speed.
Converting means for converting parallel n-frame or n-field images using at least n-1 frame or n-1 field image signal storage means, and n-frame or n-field obtained in parallel by the converting means Image signal output means for adding and averaging the images of 1 to output as an image signal of one frame or one field, thereby eliminating all image data of the image signals reproduced at high speed. Can be played at high speed. Further, the editing apparatus can check the contents of all the image data at high speed, and the editing block of the image can be determined at the same time as dubbing at high speed, so that the image editing processing time can be shortened.

The conversion means uses n-1 frame memories or field memories connected in series as the image storage means, and n image signals from the input / output terminals of each memory are parallelized. Therefore, all the image data can be reproduced at high speed without thinning out the image data of the image signal reproduced at high speed.
Further, the editing apparatus can check the contents of all the image data at high speed, and the editing block of the image can be determined at the same time as dubbing at high speed, so that the image editing processing time can be shortened.

Further, the conversion means uses the image signal storage means for n frames or more or n fields or more,
The image signals are converted into parallel images of n + 1 frames or more or n + 1 fields or more, and the image signal output means adds and averages the converted images of parallel n + 1 frames or more or n + 1 fields or more to obtain one frame or one field. By outputting as an image signal, all image data can be reproduced at high speed without thinning out the image data of the image signal reproduced at high speed. Further, the editing apparatus can check the contents of all the image data at high speed, and the editing block of the image can be determined at the same time as dubbing at high speed, so that the image editing processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an image editing system using a video signal processing device according to the present invention.

FIG. 2 is a diagram showing a schematic configuration of a video signal processing device according to the present invention.

3 is a circuit diagram of the memory circuit 12 and the frame operation device 1 of FIG.
3 is a diagram showing an example of a detailed configuration of the image output interface unit 3 and the image output interface unit 14. FIG.

FIG. 4 is a diagram showing the timing of each signal in the configuration of FIG.

[Explanation of symbols]

 11 --- Compression decoder 12 --- Memory circuit 13 --- Frame arithmetic unit 14 --- Image output interface unit 21, 22, 23-Frame Memory 24 ... Adder 25 ... Divider 26 ... Divider 27 ... Divider

Claims (3)

[Claims] 1. A video signal processing device for processing an image signal reproduced at n times speed and supplying the processed image signal to an image display device, wherein at least images of consecutive n frames or n fields of the image signal reproduced at n times speed are Conversion means for converting into parallel n-frame or n-field images using the n-1 frame or n-1 field image signal storage means, and n frames or n obtained in parallel by the conversion means.
A video signal processing device, comprising: an image signal output means for adding and averaging field images to output as an image signal for one frame or one field. 2. The conversion means uses n-1 frame memories or field memories connected in series as the image storage means, and n image signals from input / output terminals of each memory are parallelized. The video signal processing device according to claim 1, wherein the video signal processing device is taken out. 3. The conversion means converts the image signal storage means into an image of n + 1 frames or more or n + 1 fields or more in parallel by using n frames or more or n fields or more, and the image signal output means is 2. The video signal processing apparatus according to claim 1, wherein the converted parallel images of n + 1 frames or more or n + 1 fields or more are averaged and output as an image signal of one frame or one field.