JP3276858B2 - Digital still camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital still camera for compressing image data obtained by A / D conversion of a video signal from an image pickup device, recording the data in a semiconductor memory, and reproducing the data.

[0002]

2. Description of the Related Art A digital still camera, like a video camera, obtains a single image signal using an image sensor such as a CCD, digitizes the image signal, and records and holds the image signal on a medium such as a semiconductor memory. Equipment.

[0003] One of the characteristics of ordinary silver halide cameras is that they can be reproduced on the spot without going through a process such as development. The reproduction is performed by displaying the image on a liquid crystal display device built in the main body or outputting the video signal and displaying the video signal on an external monitor.

Next, a circuit block of a conventional digital still camera having a liquid crystal display device will be described with reference to FIG.
An imaging signal from the CCD 1 serving as an imaging device is a CDS (CoS
rrelated Double Sampling) / The video signal is sample-holded and level-adjusted by the AGC circuit 2, and the A / D
The data is converted by the converter 3 into digital data. The digitized image data includes three color signals, RGB and YUV.
The signal processing circuit 4 performs signal processing for obtaining such a signal, and the image compression circuit 5 compresses the data amount.
The compressed image data is recorded in the image memory 6.

The image compression circuit 5 performs image compression according to the JPEG standard. In this JPEG image compression, 8 × 8 pixels are divided into one block,
A series of processes of two-dimensional DCT (discrete cosine transform), quantization, and two-dimensional Huffman coding are executed in block units, and finally obtained compressed image data is stored in the image memory 6.

On the other hand, at the time of reproduction, the compressed image data extracted from the image memory
And is returned to the original image data.

[0007] In the case of single image reproduction in which one image is reproduced using the entire screen, the control circuit 13 controls reading of the image memory 6 and switches the two switches S1 and S2 to the contact b to expand the image. The image data for one sheet is sent to the display memory 11, and the liquid crystal display device 12 displays the contents of the display memory 11.

In the case of multi-image reproduction in which a plurality of images are divided into screens and reproduced at the same time, the control circuit 13 switches two switches S1 and S2 to a contact a, and outputs the expanded image data to a pixel number reduction circuit 14 Send to Pixel number reduction circuit 14
Is reduced by thinning out the number of pixels of the image data depending on the number of images to be displayed at the same time, and is sent to the image arrangement circuit 15. The image arrangement circuit 15 sequentially arranges the sequentially transmitted image data with the reduced number of pixels, for example, from the upper left, and creates one screen on the display memory 11. Hereinafter, similarly, the liquid crystal display device 1
2 displays the contents of the display memory 11, whereby a plurality of images are reproduced simultaneously by screen division.

FIG. 6 shows an example of a screen for reproducing a plurality of images. Here, 9 is displayed on the display screen 12A of the liquid crystal display device 12.
The images P1 to P9 are simultaneously reproduced and displayed. In this case, the pixel number reduction circuit 14 thins out pixels from the input original image data by a quarter in both the vertical and horizontal directions, and the image arrangement circuit 15 arranges the pixels sequentially with gaps in the upper, lower, left, and right directions.

[0010]

Normally, the time required for a reproducing operation in a digital still camera is substantially governed by the time required for image expansion to restore compressed image data. Therefore,
In the configuration of the related art, at the time of reproducing a plurality of images, the same decompression process as that of the single image reproduction is performed for all the images to be reproduced and displayed.
In addition, since the number of pixels is reduced and the arrangement process is performed, there is a problem that the time required for completing a reproduced image becomes longer in proportion to the number of simultaneously displayed images.

According to the present invention, a video signal from an image sensor is converted to an A / A signal.
An object of the present invention is to reduce the time required for reproducing a plurality of images in a digital still camera that compresses image data obtained by D-conversion and records the data in a semiconductor memory or the like.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a digital still camera, comprising: image data generating means for A / D converting a video signal from an image sensor to generate image data; First compression means for compressing image data to create compressed image data, compressed image recording means for recording the compressed image data on a recording medium, and reduction for thinning out pixel data from the image data to create reduced image data Image data creating means, reduced image recording means for recording the reduced image data on the recording medium, and a plurality of images for producing one image signal using a plurality of arbitrary reduced image data reproduced from the recording medium Reproduction means.

Further, the reduced image recording means includes second compression means for compressing the reduced image data.

Further, the data compression method in the first compression means and the data compression method in the second compression means are the same.

Further, one compression means is used as the first compression means or the second compression means by time division.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those of the above-described prior art shown in FIG. FIG. 1 is a circuit block diagram of a digital still camera according to a first embodiment of the present invention. In the figure, the output of the signal processing circuit 4 is compressed by an image compression circuit 5 in the same manner as in the prior art, and is recorded in the image memory 6 as compressed image data. The number of pixels is reduced according to the required number (9 in this embodiment), and the reduced image data is obtained. The reduced image data is compressed in accordance with the JPEG standard by the image compression circuit 8 in the same manner as the image compression circuit 5, and is recorded on the image memory 6 in addition to the corresponding compressed image data.

That is, as shown in the memory address map shown in FIG. 2, the image memory 6 has storage areas A1, A2 to A9 for compressed image data and storage areas A1 for reduced image data.
1, A21 to A91 are provided and each data is stored.
The storage area A0 stores the start address of each storage area and index information indicating the presence or absence of data. The index information is used when the control circuit 13 reads data from the image memory 6. Also, the illustrated symbols such as stars indicate an example in which the stored data is data for obtaining the multi-image reproduction screen shown in FIG.

In the image memory 6, the storage areas A1, A2 to A9 for compressed image data and the storage areas A11, A21 to A91 for reduced image data need not be provided at adjacent positions as shown in FIG. Needless to say, the storage area for the compressed image data and the storage area for the reduced image data may be provided at separate positions.

When reproducing one image, the original non-reduced image data is read from the image memory 6, expanded by the image expansion circuit 9, and returned to the original image data. Then, the control circuit 13 switches the two switches S1 and S2 to the contact b, and the reproduction display is performed as in the related art.

When reproducing a plurality of images, unlike the prior art,
The reduced image data is sequentially read from the image memory, and the control circuit 13 switches the two switches S1 and S2 to the contact a. The image arrangement circuit 15 sequentially arranges the reduced image data sequentially transmitted, and performs reproduction and display as shown in FIG.

Since the processing amount of image expansion depends on the number of pixels, the processing amount of image expansion is greatly reduced by using reduced image data instead of the original non-reduced image data. As a result, the time required for the entire multi-image reproduction is also reduced. Further, the image compression circuit 5 and the image compression circuit 8 both use JP
Since image compression according to the EG standard is performed, only one image expansion circuit 9 is required for image expansion.

Although the processing amount of image compression also depends on the number of pixels, since the compression processing is performed after the number of pixels is reduced, the increase in the processing amount is not so large.

Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment shown in FIG. 1 in that the image compression circuit 8 is omitted, the input is switched by the switch S3, and the image compression circuit 5 is used in a time-division manner. That is, both the image data from the signal processing circuit 4 and the reduced image data from the pixel number reduction circuit 7 are compressed by the image compression circuit 5. The same parts as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the detailed description is omitted.

Next, a third embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment shown in FIG. 1 in that the image compression circuit 8 is omitted and the reduced image data is stored in the image memory 6 without data compression. Therefore, since the image decompression circuit 9 does not need to be used at the time of reproducing a plurality of images, the plurality of images can be reproduced in a shorter time. Further, the reduced image data is smaller than the original image data, and the storage area in the image memory 6 does not become so large without compression. The same parts as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the detailed description is omitted.

Although the embodiments of the present invention have been described above, the image memory 6 in each embodiment has a capacity to store compressed image data and reduced image data for each of nine or more images. It goes without saying that arbitrary reduced image data can be sequentially read out by the circuit 13 and displayed on the liquid crystal display device 12. In each embodiment, the signal processing circuit 4, the image compression circuit 5, the pixel number reduction circuit 7, the image compression circuit 8, the image decompression circuit 9, the image arrangement circuit 10, and the control circuit 13 are configured by software in a microcomputer. May be.

[0026]

As described above, according to the present invention, the time required for reproducing a plurality of pictures can be shortened, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

FIG. 2 is an address map of an image memory.

FIG. 3 is a circuit block diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit block diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit block diagram showing a conventional technique.

FIG. 6 is an explanatory diagram showing an example of a screen for reproducing a plurality of images.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CCD 3 A / D converter 5 Image compression circuit 6 Image memory 7 Pixel number reduction circuit 8 Image compression circuit 9 Image expansion circuit 10 Image arrangement circuit 12 Liquid crystal display device 13 Control circuit

Claims (4)

(57) [Claims] 1. An image data creating means for A / D converting a video signal from an image sensor to create image data; a first compressing means for compressing the image data to create compressed image data; Compressed image recording means for recording image data on a recording medium; reduced image data creating means for creating reduced image data by thinning out pixels from the image data; and reduced image recording means for recording the reduced image data on the recording medium A digital still camera, comprising: a plurality of image reproducing means for generating one image signal using a plurality of arbitrary reduced image data reproduced from the recording medium. 2. The digital still camera according to claim 1, wherein said reduced image recording means includes second compression means for compressing said reduced image data. 3. The digital still camera according to claim 2, wherein a method of compressing data in said first compression means and said second compression means is the same. 4. The method according to claim 1, wherein one compression means is divided into the first compression means by time division.
The digital still camera according to claim 2, wherein the digital still camera is used as a compression unit or a second compression unit.