JP3519846B2 - Still image generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording medium on which a digital video signal is compressed and recorded, and reads out the video signal recorded on the recording medium. And a circuit for generating a still image. 2. Description of the Related Art HD (High Definition) digital VCR
The council is studying the standardization of a digital VTR for recording and reproducing a video signal as digital data. Here, a video signal on which image compression has been performed by DCT (Discrete Cosine Transform) in units of 8 × 8 pixels adjacent to each other in luminance or color difference is recorded on the magnetic tape. FIG. 5 shows a signal recording system of a digital VTR. The video signal is first sent to the intra-frame shuffle circuit.
After being sent to (11) and one frame is stored in the circuit, shuffling is performed to stochastically equalize the information amount in the next image compression. Specifically, a rectangular video portion of 8 pixels × 32 pixels of a luminance signal is defined as one macroblock, and macroblocks are respectively collected from five dispersed positions on one screen. The shuffled original video signal V1 is sent to an image compression circuit (12), and is compressed to a fixed code amount using the above five macroblocks as one unit of compression. In image compression, a block of 8 × 8 pixels is extracted from a macroblock, subjected to DCT, and further subjected to quantization and variable length coding. At this time, 5
The code amount is controlled such that the code amount obtained by combining the two macroblocks becomes constant after the variable length coding. [0005] By the way, in a normal television receiver, since interlaced scanning is performed, the odd field and the even field are spatially interpolated with each other, but are temporally different from each other. In the stationary part of the screen, the image of the odd and even fields has a high correlation, and it is more efficient to compress the odd and even fields as a frame image, Since the correlation between the odd-numbered field and the even-numbered field is low, it is more efficient to separately compress both fields. Therefore, as shown in FIG. 6, the image compression circuit (12) includes a first DCT circuit (16) for performing DCT on a data group having a size of 8 × 8 pixels in a frame, and a first DCT circuit (16) in a field. A second DCT circuit (17) for separately applying DCT to two data groups each having a size of 8 pixels × 4 pixels, and a field correlation determination circuit (18) for determining the degree of correlation between fields of the original video signal V1 Are provided in parallel, and the changeover switches (19) connected to the output terminals of the DCT circuits (16) and (17) are switched by the frame / field bits obtained from the field correlation determination circuit (18). The output terminal of the changeover switch (19) is connected to a quantization / variable length coding circuit (20). The output signal of the quantization / variable-length coding circuit (20) is supplied to a mixing circuit (21) and mixed with a frame / field bit from a field correlation determination circuit (18), and is output as a compressed video signal V2 in FIG. To the error correction code adding circuit (13) shown in FIG. The compressed video signal V2 is rearranged by an error correction code adding circuit (13) in the order in which it is to be recorded on the tape, an error correction code is added thereto, and furthermore, a synchronization signal adding circuit (1
The synchronization signal is added in 4), and after that, the modulation necessary for tape recording is performed via the modulation circuit (15), and then sent to the magnetic head and recorded on the magnetic tape. FIG. 7 shows a signal reproducing system of a digital VTR. The signal read from the magnetic tape by the magnetic head was first subjected to amplification and equalization processing in the signal processing circuit (22), and further subjected to demodulation and synchronization detection processing in the demodulation and synchronization detection circuit (23). Thereafter, the signal is supplied to an error correction circuit (24), where error detection and error correction are performed. For the portion where error correction was not possible in the error correction circuit (24), an interpolation process is performed in a subsequent-stage error interpolation circuit (25) using the data of the previous frame. The original video signal V3 obtained in this way is supplied to the image decompression circuit (26), and undergoes a process reverse to the process at the time of image compression, and is restored to the original video signal. That is, in the image decompression circuit (26), FIG.
As shown in the figure, the original video signal V3 is input to the variable-length code decoding / dequantization circuit (28), and at the subsequent stage of the circuit (28),
A first inverse DCT circuit (29) for performing inverse DCT on a data group having a size of 8 pixels × 8 pixels in a frame and two data groups having a size of 8 pixels × 4 pixels in a field A second inverse quantization circuit (30) that performs inverse DCT separately is connected in parallel. The original video signal V3 is supplied to a frame / field bit extraction circuit (31), whereby the frame / field bits extracted from the original video signal V3 are supplied to the output terminals of the inverse DCT circuits (29) and (30). The supplied changeover switch (32) is supplied to the changeover switch (3
The switching of 2) is performed. [0010] As a result, image expansion is performed in the frame for a block that has undergone image compression in the frame, and image expansion is performed in the field for a block that has undergone image compression in the field. Will be.
The decompressed video signal V4 obtained in this way is supplied to the intra-frame deshuffling circuit (27) in FIG. 7, and after being subjected to deshuffling for returning the data of each block to the original position on the screen, a normal Display device as video signal
(Not shown). By the way, in a digital VTR as described above, a still image can be generated as follows. That is, after data for one frame is sent to the intra-frame deshuffle circuit (27) shown in FIG. 7, the running of the magnetic tape is stopped, and the input of data to the intra-frame deshuffle circuit (27) is also stopped. . Then, of the data for one frame stored in the intra-frame shuffling circuit (27), the video data of one of the odd and even fields is repeatedly output to the display device at a field cycle. As described above, the still image is generated using only one of the fields because the odd field and the even field in one frame have a temporal difference, so that the moving object on the screen is generated. Is present, if the odd field and the even field are alternately output, the image of the subject is blurred, resulting in a still image that is difficult to see. However, in a still image based on only one field in one frame, the vertical resolution of the still image portion is two or more.
There is a disadvantage that it is reduced by a factor of one. As described above, when a still image based on only one field in one frame is adopted in a still image for a screen in which a still image portion and a moving image portion are mixed, the still image However, when a still image based on two fields in one frame is adopted, blur occurs in a moving image portion, and there is a problem that improvement in vertical resolution and elimination of blur are incompatible. there were. It is an object of the present invention to provide a still picture generating circuit which can obtain a high vertical resolution for a still picture part and can generate a still picture without a blur for a moving picture part. . A still image generation circuit according to the present invention divides one screen into a plurality of blocks when recording a video signal. When the correlation between two consecutive fields of the video signal of each block is higher than a predetermined threshold, the video signal is compressed for each block in the frame, and when the correlation is lower than the predetermined threshold, the field signal is compressed. The video signal is compressed for each block in the block, and a frame / field bit indicating whether each block is compressed in the frame or in the field is recorded together with the compressed video signal of each block. As a target, a circuit for reading an original video signal from the recording medium and generating a still image, wherein: (a) the circuit is recorded on the recording medium Signal reading means for reading an original video signal; (b) extracting frame / field bits from the read original video signal, and subjecting the original video signal of each block to image expansion processing according to the frame / field bits; The decompressed video signal obtained in this way is
(C) a frame / field bit memory capable of storing one frame / field bit output from the image decompression means, and (d) output from the image decompression means. A frame memory capable of storing one frame of decompressed video signal, (e) a frame / field bit memory and write control means for controlling data writing to the frame memory, and (f) a frame / field bit memory. The readout of the expanded video signal from the frame memory is controlled for each screen area composed of one or a plurality of blocks according to the frame / field bits set, and the frame / field bits indicating that the correlation between the fields is high predominate. For screen areas that are Reads the field extension video signal alternately in the field period, the screen area frame / field bits predominates indicating that low correlation between fields,
There is provided a read control means for repeatedly reading out the decompressed video signal of the field fixed to any one at a field cycle. In the still picture generation circuit, when the still picture generation command is issued, the writing control means writes the frame / field bits into the frame / field bit memory and writes the expanded video signal into the frame memory. By controlling the writing, one frame of the expanded video signal is stored in the frame memory, and one frame / field bit is stored in the frame / field bit memory. Stopped. Next, the reading control means reads out the expanded video signal from the frame memory based on the frame / field bits stored in the frame / field bit memory for each screen area composed of one or a plurality of blocks. Control. For example, in the process of reading data on one horizontal scanning line constituting an odd field, for a screen area in which frame / field bits indicating high correlation between fields are predominant, an expanded video signal of the odd field is first read, For a screen area in which frame / field bits indicating low correlation between fields are predominant, an expanded video signal of a field (for example, an odd field) fixed to one of them is read. Thereafter, in the process of reading data on one horizontal scanning line constituting the even field, for a screen area in which frame / field bits indicating high correlation between fields are predominant, the expanded video signal of the even field is read, Frame indicating low correlation between fields /
For a screen area in which field bits are dominant, an expanded video signal of a field (odd field) fixed to the one is read. It should be noted that the superiority of the field correlation of the frame / field bits in each screen area can be easily determined by, for example, the average value of the frame / field bits of each block included in the screen area. As a result, for a screen region having a high correlation between fields, a still image based on two fields (one frame) is generated, the vertical resolution is improved, and a screen region having a low correlation between fields is generated. For, a still image based on only one of the fields is generated, and blurring of a moving image is prevented. According to the still picture generation circuit of the present invention,
A high vertical resolution can be obtained for a still image portion, and a still image without blur can be generated for a moving image portion. Hereinafter, embodiments of the present invention applied to a digital VTR will be described in detail with reference to the drawings. Note that the signal recording system of the digital VTR is the same as the conventional configuration shown in FIGS. 5 and 6, and two consecutive 2 × 8-pixel blocks (DCT blocks) serving as units for performing DCT.
When the correlation between the fields is higher than a predetermined threshold, the video signal is compressed in the frame. When the correlation is lower than the predetermined threshold, the video signal is compressed in the field, and each block is compressed in the frame. Frame / field bits indicating which of the fields is compressed are recorded on the magnetic tape together with the compressed video signal of each block. FIG. 1 shows a signal reproducing system of a digital VTR according to the present invention. A signal read from the magnetic tape by the magnetic head is first sent to a signal processing circuit (1).
Undergoes amplification and equalization processing, and demodulation / synchronization detection circuit
After undergoing demodulation and synchronization detection processing in (2), the error correction circuit
The data is supplied to (3) to be subjected to error detection and error correction.
For the portion where the error correction cannot be performed by the error correction circuit (3), an interpolation process is performed by the subsequent error interpolation circuit (4) using the data of the previous frame. The original video signal V3 obtained in this way is supplied to an image decompression circuit (5),
The image is restored to the original video signal by receiving a process reverse to the process at the time of image compression. The structure of the image decompression circuit (5) is the same as that of the conventional image decompression circuit (26) shown in FIG. The blocks which have been subjected to image compression in the field are subjected to image expansion in the field. The decompressed video signal V4 and the frame / field bits obtained in this manner are supplied to the intra-frame deshuffle circuit (6) in FIG. 1, and subjected to deshuffling for returning the data of each block to the original position on the screen. After that, it is output to a display device (not shown) as a normal video signal. The intra-frame deshuffling circuit (6) has a function for deshuffling as in the prior art, and has a circuit configuration for generating a still image, as shown in FIG. A frame / field bit memory (10) capable of storing output frame / field bits for one frame, and an expanded video signal V4 for one frame output from the image expansion circuit (5). And a write control circuit (8) for supplying a write address to a frame / field bit memory (10) and a frame memory (7).
And a read control circuit (9) for supplying a read address to the frame / field bit memory (10) and the frame memory (7). The write control circuit (8) writes one frame of the expanded video signal V4 to the frame memory (7) in response to the still image generation command, and simultaneously writes one frame / field bit of the frame / field. After writing to the bit memory (10), writing of data to both memories is stopped. In this process, the write control circuit (8) generates a video signal write address corresponding to the position of the block on the screen based on the synchronization signal or the number of the reproduced block, and generates the frame memory (7). The video signal sent in block units is written at a position corresponding to the screen of (1). The write control circuit (8) generates a frame / field bit write address corresponding to the position of the block on the screen for the frame / field bit for each block transmitted simultaneously, and A frame / field bit for each block is written at a position corresponding to the screen of the / field bit memory (10). Thereafter, the read control circuit (9) sequentially reads the frame / field bits for each block stored in the frame / field bit memory (10),
According to the value, reading of the expanded video signal from the frame memory (7) is controlled for each block. For example, in the process of reading data on one horizontal scanning line that constitutes an odd field, for a block in which a frame / field bit indicating high correlation between fields is written, the expanded video signal of the odd field is read. ,
For blocks in which frame / field bits indicating low correlation between fields are written,
The decompressed video signal of one of the fixed fields (for example, an odd field) is read. After that, in the process of reading data on one horizontal scanning line that should form an even field, for a block in which a frame / field bit indicating a high correlation between fields is written, the expanded video signal of the even field is read. reading,
For blocks in which frame / field bits indicating low correlation between fields are written,
The decompressed video signal of the fixed one field (odd field) is read. For example, as shown in FIG. 3, when a DCT block 1 having a high correlation between fields and a DCT block 2 having a low correlation between fields are adjacent to each other, an odd field is formed as shown in FIG. In the process of reading the data on the odd lines to be read, the DCT block 1 reads the expanded video signals of the odd lines, and then the DCT block 2 reads the expanded video signals of the odd lines. next,
As shown in FIG. 4B, in the process of reading the data on the even lines that should form the even field, the DCT block 1
After reading the expanded video signal of the even line,
In the T block 2, the extended video signal of the odd line is read. As a result, DC having a high correlation between the fields
As for the T block 1, a still image based on two fields (one frame) is generated, the vertical resolution is improved, and the DCT block 2 with low correlation between fields is generated.
For, a still image is generated based only on the odd-numbered fields, and blurring of a moving image is prevented. Therefore, when generating a still image for a video in which the subject moves with the background of the still image, a high vertical resolution is maintained for the background portion, and a still image without blur is obtained for the moving subject. become. According to the circuits shown in FIGS. 1 and 2, the degree of correlation between the fields of each DCT block is determined using the frame / field bits used for image compression and decompression. There is no need to add a special circuit for determining the correlation, and the circuit configuration is simplified. The description of the above embodiment is for the purpose of explaining the present invention, and should not be construed as limiting the invention described in the claims or reducing the scope thereof.
Further, the configuration of each part of the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications are possible within the technical scope described in the claims. For example, the size of the screen area for switching between generating a still image based on two fields or generating a still image based on one field is as follows.
The method is not limited to the method in which one DCT block is used as in the above-described embodiment, and a method in which a plurality of DCT blocks are set to the size of one screen area can be adopted. In this case, it is possible to average the frame / field bits of a plurality of DCT blocks included in one screen area, and determine the level of the correlation between the fields based on the average value.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a configuration of a signal reproduction system of a digital VTR according to the present invention. FIG. 2 is a block diagram illustrating a configuration of an intra-frame deshuffle circuit. FIG. 3 is a diagram illustrating two adjacent DCT blocks. FIG. 4 is a table for explaining data read control for an odd field and an even field; FIG. 5 is a block diagram illustrating a configuration of a signal recording system of the digital VTR. FIG. 6 is a block diagram illustrating a configuration of an image compression circuit. FIG. 7 is a block diagram illustrating a configuration of a signal reproduction system of a conventional digital VTR. FIG. 8 is a block diagram illustrating a configuration of an image decompression circuit. [Description of Code] (1) Signal processing circuit (2) Demodulation / synchronization detection circuit (3) Error correction circuit (4) Error interpolation circuit (5) Image decompression circuit (6) In-frame deshuffle circuit (7) Frame memory ( 8) Write control circuit (9) Read control circuit (10) Frame / field bit memory

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-362885 (JP, A) JP-A-6-78265 (JP, A) JP-A-6-165103 (JP, A) JP-A-6-165103 350974 (JP, A) JP-A-8-317336 (JP, A) JP-A-4-86185 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5 / 91-5 / 956

Claims (1)

(57) [Claims 1] When recording a video signal, one screen is divided into a plurality of blocks, and the video signal of each block is continuous.
When the correlation between two fields is higher than a predetermined threshold,
The video signal is compressed for each block in the frame, and
If the function is lower than a predetermined threshold,
The video signal is compressed for each block, and each block is
Indicates whether compression is performed within the frame or within the field.
The frame / field bits passed are compressed by each block.
For recording media recorded with video signals,
A circuit for reading an original video signal from the recording medium to generate a still image, comprising: signal reading means for reading the original video signal recorded on the recording medium; and a frame / field bit from the read original video signal.
And extract the frame to the original video signal of each block.
Image expansion processing according to the system / field bits,
The decompressed video signal obtained in this way is
Image decompression means for outputting the image data together with the blank bit, and one frame / frame output from the image decompression means.
Frame / frame that can store field bits
Field bit memory , a frame memory capable of storing one frame of decompressed video signal output from the image decompression means, a frame / field bit memory, and a frame memory
Write control means for controlling the writing of data to the memory, and a file stored in the frame / field bit memory.
Frame memory depending on the frame / field bit
Read out the expanded video signal from one or more blocks
Control for each screen area, and high correlation between fields
Frame / field bit that indicates
For screen area, odd and even fields
Read out the expanded video signal alternately in the field cycle,
Frames / fields indicating low correlation between fields
A still image generation circuit comprising: read control means for repeatedly reading out a decompressed video signal of a field fixed to one of the screen areas in a field cycle in which a field bit is dominant .