KR970004746A

KR970004746A - Plasma Display Panel TV Frame Memory Device

Info

Publication number: KR970004746A
Application number: KR1019950017942A
Authority: KR
Inventors: 박원정
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1995-06-28
Filing date: 1995-06-28
Publication date: 1997-01-29

Abstract

본 발명은 플라즈마 디스플레이 패널 텔레비젼의 프레임 메모리장치에 관한 것으로, 메모리선택 제어신호에 의해 영상데이타를 라이트 또는 리드하는 제1프레임 메모리(33); 메모리선택 제어신호에 의해 영상데이타를 리드 또는 라이트하는 제2프레임 메모리(34); 및 상기 메모리선택 제어신호에 따라 상기 제1프레임 메모리(33) 혹은 제2프레임 메모리(34)의 출력중 하나를 선택하여 출력하는 데이타 선택부(37)로 구성되어 교번적으로 리드, 라이트를 수행하고, 어느 한 출력만 선택하므로써 영상데이타를 연속적으로 제공함과 아울러 처리속도를 향상시킬 수 있는 효과가 있다.The present invention relates to a frame memory device of a plasma display panel television, comprising: a first frame memory (33) for writing or reading image data in response to a memory selection control signal; A second frame memory 34 which reads or writes image data in response to a memory selection control signal; And a data selector 37 which selects and outputs one of the outputs of the first frame memory 33 or the second frame memory 34 according to the memory selection control signal. By selecting only one output, the video data can be continuously provided and the processing speed can be improved.

Description

Plasma Display Panel TV Frame Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 프레임 메모리의 블럭도, 제4도의 (가) 내지 (마)는 본 발명에 따른 장치의 동작을 설명하기 위해 도시한 타이밍도이다.3 is a block diagram of a frame memory according to the present invention, and (a) to (e) of FIG. 4 are timing diagrams for explaining the operation of the apparatus according to the present invention.

Claims

After demodulating the received video signal, it converts it to digital, receives a memory address and a memory selection signal from the write and read address generator 25 and the control signal generator 27, and alternately converts the digitally converted video data into a frame memory. 13. A PDP television for displaying and reading image data for display on a PDP, the frame memory comprising: a first frame memory (33) in which the frame memory writes or reads image data in response to the memory selection signal; A second frame memory 34 which reads or writes image data in response to the memory selection signal; And a data selector (37) for selecting and outputting one of the outputs of the first frame memory or the second frame memory according to the memory selection signal.

The frame memory device of claim 1, wherein the data selection unit is implemented as a multiplexer.

※ Note: The disclosure is based on the initial application.