JPS5837688A - Reflesh memory access system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a refresh memory access method, in particular, a refresh memory (ORT buffer) access method in which a macroprocessor and an ORT controller alternately use time sharing between a microprocessor cycle and an OIL T controller cycle. In the refresh memory access method, when a microprocessor requests a circular access to the refresh memory during period 111 of the 0ILT controller cycle, data transfer is possible without stopping the microprocessor. This relates to the access method of the configured refresh memory.

Conventionally, refresh memory contention in an ORT display device, which occurs when a CRT controller attempting to refresh the screen and a microprocessor attempting to update image data access the refresh memory simultaneously, has been solved using a video TLAM method. D
MA (formerly rect mem.

-ry access). In the video RAM method where the ORT controller and the microprocessor share the refresh memory using a multiplex circuit and tri-state buffer, the refresh memory is separated from the ORT controller when the microprocessor accesses it, causing stripes and terras on the screen. There was a drawback that appeared.

On the other hand, in the DMA method where the refresh memory resides in the microprocessor's memory space, the microprocessor is forced to stop every time the CRT controller requests access to the refresh memory, which slows down the microprocessor's processing speed. There was a drawback.

One object of the present invention is to solve the above-mentioned drawbacks, and includes a data buffer for storing image data to be transferred between a microprocessor and a refresh memory, and an address register for storing the address thereof.
During an OLT controller cycle when the ILT controller requests access to refresh memory,
When the microprocessor requests access to write image data to be updated to the refresh memory, the image data is transferred to the data buffer and stored in the data buffer when the next microprocessor cycle arrives. It is an object of the present invention to provide a refresh memory access method that prevents stripes and terracing on the screen and avoids stopping the microprocessor by writing the image data to be updated into the refresh memory. Therefore, the refresh memory access method of the present invention includes a refresh memory, a microprocessor that updates the image data in the refresh memory, and periodically accesses the image data stored in the refresh memory to refresh the screen display. Equipped with an ORT controller,
The macroprocessor and the ORT controller alternately access the refresh memory in the time sharing between the microprocessor cycle and the ORT controller cycle. a data buffer for storing image data to be transferred to a data buffer and an address register for storing data at the address; a control device for controlling the data buffer and the address register in response to the microprocessor or ORT controller cycles; and a data selector that outputs a selection signal for a RAM chip constituting the memory, so that when the microprocessor requests write access to the refresh memory during the ORT controller cycle, the microprocessor is not stopped. II should be updated! It is characterized by being configured to be able to transfer ll image data. This will be explained below with reference to the drawings.

Fig. 1 is an explanatory diagram explaining the access cycle of the beam freshet memory, Fig. 2 is an example configuration of the refresh memory access method according to the present invention, and Fig. 183 is an explanatory diagram illustrating the access cycle of the beam freshche memory. 1 shows an example configuration of the case.

In the explanatory diagram illustrating the access cycle of the refresh memory shown in FIG. 1, a microprocessor tries to update image data in the refresh memory, an ORT controller tries to refresh the screen display by periodically accessing the image data, and are accessed alternately in a time-sharing manner. A switching control signal for switching this cycle is generated from a dot counter of a synchronizing signal generating circuit (not shown). An 8-dot (1-byte) clock is considered as one cycle for accessing the fresh memory between the microprocessor and the 0T controller, and the first half cycle of 4 dots is a microprocessor cycle in which the microprocessor has access. The latter half cycle of 4 dots is the 01LT controller cycle, which the 0ITT controller has access rights 11 to.

The OIT T controller refreshes the 8 dots worth of image data to be displayed next during the ORT controller cycle in the second half of the description from the memory to the E stomach 41 L screen.1. Therefore, O
The R'l' controller does not access the refresh memory during the microprocessor cycle in which the microprocessor has the right to access the refresh memory, and must always access the I+!1.1 image in the OIti'' controller cycle. Refreshing is performed, and no stripes or unevenness appear on the field.

On the other hand, since the clock of the microprocessor is not synchronized with the memory d control signal, the timing of the access request to the refresh memory of the microprocessor and the above-mentioned microprocessor cycle, which causes the image data to change, 1. Since the timing of the II side 1 signal is not synchronized, for example, at 011°T': 5 dot clock during the 7 controller cycle period (2) when a refresh memory access request is generated from the If!, lf fψ data and the data at that address are transferred to the data buffer and address register to be described. (The 1u1 image data is transferred to the refresh memory (=transferred and replaced.) In this way, requests for access to the refresh memory from the microprocessor are processed during the ORT controller cycle, and a shutdown of the microprocessor is avoided. It looks like it's going on (two times).

FIG. 2 shows the configuration of an embodiment of the refresh memory access method according to the present invention, in which reference numeral 1 is a microprocessor, 2 is a refresh memory, 3 is a □RT controller, 4 is an address register, and 5 is a 6 is a data buffer, 7 is an address decoder, 8 is a control device, 9 is a chip select register, 10 is a data selector, 11 is an address buffer, and 12 is a parallel-to-serial converter (representing nine units, respectively).

The microprocessor 1 requests the refresh memory 2 to transfer image data.

The refresh memory 2 is generally referred to as a 0T buffer, and is a RAM that stores image data for one screen of the ORT display device. Based on the ORT controller 3 accessing the refresh memory 2 (2) to request data transfer and refresh the screen, the microprocessor 1 and O This memory competes with the T controller 3.

The ILT controller 3 sequentially accesses the image data stored in the refresh memory 2, and outputs a switching control signal for controlling the switching between the microprocessor cycle explained in Figure 1 and the JILT controller cycle. This is a control device that performs signal processing on the image data read out from the parallel-to-serial converter 12 and outputs it as a video signal.

The control device 8 includes an address register 4, a data buffer 5,
6. A control device that controls each writing or reading timing of the chip select register 9 and the like.

The data selector IO alternately selects the signal from the chip select register 9 or the 0T controller 3 according to the switching control signal, and selects the signal from the RAM of the refresh memory 2? It outputs a signal specifying the knob.

Next, the operation of the refresh memory access method according to the present invention will be explained as follows.

When the microprocessor f1 attempts to access the refresh memory 2 to update the image data during the 0rLT controller cycle, control signals are sent from the control unit [8 to the address register 4 and data buffer 76, respectively. As a result, the image data to be updated is transferred to the data buffer 6, and the data at that address is stored in the address register 4.

When time has passed and the -1-goRT controller cycle ends and the microprocessor cycle begins, the CRT controller 3 issues a switching control number I/H to the data selector 10 and sets it in the chip select register 9. Memory 2 E It A M
The selected f number is output from the data selector 10. Therefore, the content stored in the data buffer 6 at the address stored in the AT/S register meta 4, that is, the song 1 image data to be recorded from the microprocessor 1 is stored in the refresh memory 2. .

Also, microprocessor 1 performs one song for refresh memory 2 during 1ul1 of the microprocessor cycle.
When an attempt is made to access the normal data for updating, the data to be updated from the microprocessor 1 is immediately written into the refresh memory 2 via the data buffer 6.

For example, when there is no request from the microprocessor 1 to transfer image data to be refreshed, the It AM selection signal of the refresh memory 2 is not set from the step select register 9 during the microprocessor cycle, and the slave Therefore, the data selector 10 continues in a state in which it does not issue the IL AM selection signal to the refresh memory 2.

In this way, the microprocessor 1 transfers image data to the refresh memory 2 during the OIt1' controller cycle! Even if an attempt is made to access the new image data, the microprocessor 1 can transfer the image data to the data buffer 6, so a stop signal is sent to the microprocessor 1 from the bell th signal generation circuit (not shown). It is not output, so the microprocessor 1 can perform the next process without stopping.

Next, the access of the ORT controller 3 to the refresh memory 2 will be described. When the 0ILT controller cycle comes, the address of the image data of the screen to be refreshed from the ott'r controller 3 is set in the address buffer 11. Based on the signal from the OTL'r controller 3, the e-data selector 10 outputs a RAM selection signal to the flexible memory 2.
Image data at the address set in the address buffer 11 is read from the refresh memory 2.

This image data is converted into a serial signal by a parallel partial column converter 12 to become a video signal, which refreshes the screen of a display device (not shown).

Note that when the microprocessor 1 reads image data stored in the refresh memory 2, if the microprocessor 1's access request to the refresh memory 2 is during the 0TLT controller cycle, the microprocessor 1 stops ( 11) Get kicked.

Then, in the next microprocessor cycle, a reset signal is sent to the stopped microprocessor 1, and the microprocessor 1 is activated. As a result, the refresh memory 2 is accessed using the address set in the address register 4. At this time, the chip select register 9 is set with the ILAM''fRAM selection signal that constitutes the refresh memory 2, and this signal is output from the data selector 10 to the refresh memory 2 as a RAM selection signal. The image data is read out from the refresh memory 2, and the control number 46 of the control device 8 causes the data buffer 5: 1,
The image data stored in the data buffer 5 is read out and transferred to the microprocessor 1.

FIG. 3 shows the configuration of an embodiment in which a plurality of ORT buffers are provided in the refresh memory.
4.5, 7 to 11 correspond to those in FIG. 13
is refresh memory, 14°15 is ORT buffer,
16 is a data register, 17.18 is a data buffer,
19.20 represents a parallel-to-serial converter.

The refresh memory 13 is composed of two memories, ORT buffers 14 and 15, and is a memory in which the microprocessor 1 and the ORT controller 3 compete with each other.

0rtT' buffer 14.15 is 1+ of ORT display device
This is a RAM that stores each image data, and for example, the screen of the ORT display device is "black".

When displayed with 3 brightness levels: "White - 1" and "Medium", ORT
The buffer 14 stores image data represented by "white" brightness, and the ORT buffer 15 stores image data represented by "medium" brightness.
, M.

ORT buffer 14゜15゜2 in refresh memory 2
The operation when there is one is as follows.

If the microprocessor 1 attempts to access the refresh memory 2 during the Oit T controller cycle to obtain the history J1 of the image ψ data, the control
41 device 8 to address register 4, data register 1
The two image data to be updated by controlling each of the addresses 6 and 6 are transferred to the data register 16, and at the same time, the data at that address is stored in the address register 11. And-
1- II to be updated! II image data is transferred to data buffer 1 by control signal from control 1 (,q12).
7 or data buffer 18 immediately. For example, 1+1+ to be renewed! If the image data is data to be displayed with "white" brightness, it will be transferred to the data buffer 17 (2). Also, when the microprocessor 1 attempts to access the refresh memory 2, the chip select from the address recorder 7 is transferred. 0 for register 9
A signal specifying the ILT buffer 14 or 0 T buffer 15 is sent, and the above specified signal is set in the chip select register 9 by the fli'l 11 signal from the 1lil (+ill device 8). If the image data to be displayed is data displayed in "white" color, the chip select register 9 is set to 0T.
A signal specifying buffer 14 is set.

When time passes and the ORT controller cycle ends and the microprocessor cycle begins, a switching control signal is issued from the OIL'r controller 3 to the data selector 1 ( ), and No. 11 set in the chip select register 9, that is, the ORT buffer. A signal specifying 14 is output from the data selector 10. Therefore 0IIT
The buffer 14 receives i+iii to be updated from the microprocessor 1 with the contents stored in the data buffer 17 at the address stored in the address register 4.
Image data has been written.

Note that the image 11 to be updated from the microprocessor 1
! If the data is displayed with "medium" brightness, the image data is stored in the data buffer 18 in advance, and a signal specifying the ORT buffer 15 is set in the chip select register 9. , when the microprocessor cycle starts, the data buffer 18 is stored at the address stored in the address register 4.
The image data to be updated from the microprocessor 1 whose contents are stored in I't is written to the ORT buffer 15.

In this way, the microprocessor 1 controls the refresh memory 2 during the ORT controller cycle.
Even if an attempt is made to access the JI 1m data to update it, the microprocessor 1 can transfer the image data to the data register 16.
Stop I (not shown): No stop signal is output from the signal generating circuit to the microprocessor 1, so the microprocessor 1 can perform the next process without stopping.

When the next ORT controller cycle comes, the ORT
The address of the image data of the art dealer to be refreshed from the controller 3 is set in the address buffer 11.

For the ORT buffers 14 and 15 specified by the data selector 10 (in the ORT controller cycle, the oa'r buffers 14 and 15 are specified at the same time), the autonomous data on the address set in the address buffer 11 is - Parallel-series foundation converter 19
, 20, respectively. Each parallel-series branch 1k
'lri 19.

The image data converted in step 20 becomes Videoi No. 1,
Both video signals are combined to refresh the virtual image on the display device.

Note that the microprocessor 1 has lI! stored in the refresh memory 2! When outputting II image data &j6, an access request to the refresh memory 2 of the microprocessor 1 is stopped during the OT (T controller cycle period).

Then, at the next microprocessor cycle, a reset signal is sent to the microprocessor 1, and the microprocessor 1 is activated. As a result, the 0ILT buffer 14 or ORT buffer 15 designated via the data selector 10 is accessed using the address set in the address register 4 by the designation signal from the chip-relevant register 9. For example, ORT buffer 1
4 is specified, the image data read from the ORT buffer 14 is stored in the data buffer 17 by the fb control signal from the control device 8, and immediately transferred to the data buffer 5. Similarly 011. When the buffer 15 is accessed, the image 1ψ data output from the CRT buffer 5 is stored in the data buffer 18 and then transferred to the data buffer 5. The data for each image per image stored in the data buffer 5 in this way is read out by the microprocessor 1 (2).

As explained above, according to the present invention, by providing a data buffer and an address register for storing data at the address between the microprocessor, the Fresco, and the memory, the microprocessor can perform image processing during the ORT controller cycle. Since the microprocessor is not stopped even when a refresh request is made to update data or a write access to the memory is requested, the processing speed of the microprocessor is improved.

Since the refresh memory is accessed alternately in a time-sharing manner between the microprocessor cycle and the OIL controller cycle, the refresh of the ORT controller is completely executed and there are no stripes or terras on the screen. Image data can be updated without appearing.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram illustrating a memory access cycle; FIG. 2 is a configuration of an embodiment of a refresh memory access method according to the present invention; FIG. This figure shows an example configuration for a case where the In the figure, 1 is a microprocessor, 2 is a refresh memory, 3 is an ORT controller, 4 is an address register,
5 is a data buffer, 6 is a data buffer, 7 is an address decoder, 8 is a control device, 9 is a chip select register, 10 is a data selector, 11 is an address buffer,
12 represents a parallel-n (J column converter), 13 represents a refresh memory, 14.15 represents an ORT buffer, 16 represents a data register, 17.18 represents a data buffer, and 19.20 represents a parallel-serial converter. Special Wr applicant: Anritsu Electric Co., Ltd. Figure 1

Claims (1)

[Claims] a refresh memory; a microprocessor that updates the image data in the refresh memory; and an ILT controller that periodically accesses the image data stored in the refresh memory to refresh the screen display. The microprocessor and the 0ILT controller are exchanged on a time-sharing basis between the microprocessor cycle and the 0ILT controller cycle! 11 in the refresh memory access method for accessing the refresh memory: a data buffer for storing 1llll image data to be transferred between the microprocessor and the refresh memory; and an address register for storing data at the address; a control device for controlling the data buffer and address register in response to a processor cycle or an OIt 'I' controller cycle; and a data selector for outputting a selection signal for the rLAM chip constituting the refresh memory; and when a microprocessor backs up a write access to the refresh memory during an ORT controller cycle, the microprocessor must be updated without being stopped.
1. An access method for a fresh memory, characterized in that it is configured to allow image data σ)111rz transmission.