JPH07311837A - Image recording device - Google Patents

Abstract

PURPOSE:To reduce the overall cost and to attain a high-speed processing in an image recording device which can perform a smoothing recording operation by enabling a CPU to carry out other processings while the smoothing arithmetic data are transferred. CONSTITUTION:An arbitration circuit 40 is placed between a control bus 50 of a CPU 20 and a control bus 60 of a page memory 30, connects together both buses 50 and 60 when an image forming device 90 does not output a read request, and disconnects the bus 60 from the bus 50 when the device 90 outputs a read request to connect the bus 60 to the device 90. Thereby, the CPU 20 can carry out other processings in parallel to each other while the smoothing arithmetic data are transferred.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus suitable for use in copying machines, printers, facsimiles, etc., and more particularly to an image recording apparatus having a function of smoothing image data. .

[0002]

2. Description of the Related Art Conventionally, as this type of image recording apparatus,
Central control unit (CP that operates according to a predetermined program)
Under the control of U), the image data for one page stored in a page memory such as a dynamic RAM (DRAM) is read line by line, and the image recording unit is operated based on this data to generate an image recording medium. There is a device for recording images on the top. In performing such image recording, it is known that the image data of the preceding and following lines are subjected to a smoothing calculation process before recording in order to smooth the lines of the image to be recorded. There is a dedicated line memory used to perform the smoothing arithmetic processing on the data of the previous line and the current line as described above, but this line memory is expensive and causes a cost increase.

Therefore, without using the expensive dedicated line memory as described above, the data required for the smoothing calculation is read from the DRAM at any time and transferred to the smoothing calculation processing section, and the smoothing calculation is performed in the processing section. There is a way.

[0004]

By the way, in the method of performing the above smoothing calculation, the CPU and the DR are conventionally used.
Since the AM is connected to the same bus, the CPU is in a waiting state during the transfer of the smoothing calculation data from the DRAM to the smoothing calculation processing unit, which is a factor that hinders the high-speed processing of the entire image recording apparatus. The smoothing calculation data is transferred according to the read request from the image recording unit.

The present invention has been made in order to solve the above-mentioned problems, and by switching the bus connection during the smoothing operation data transfer, the CPU performs other processing operations during the data transfer. It is an object of the present invention to provide an image recording apparatus that can realize the above-mentioned processing and that can be processed at low cost as a whole.

[0006]

In order to achieve the above object, an image recording apparatus according to a first aspect of the invention has a storage means for storing image data, and a smoothing calculation process for image data read from the storage means in response to a read request. Smoothing processing means, image forming means for recording image data read from the storage means and smoothed by the smoothing processing means, central control means for controlling writing of image data to the storage means, central control Means and a storage means are connected to each other for signal transmission, and the control bus on the side of the central control means and the control bus on the side of the storage means are provided separately, and are provided between these control buses. The control bus on the side of the central control unit and the control bus on the side of the storage unit are connected to each other, and when the image forming unit issues a read request, Disconnect your bus from the control bus of the central control unit side are those having a bus arbitration means for arbitrating to connect to the image forming means side.

According to the image recording apparatus of claim 2, in addition to the configuration of the image recording apparatus of claim 1, the image data read from the storage means in response to a read request from the image forming means is parallel data. Further, the image data that is smoothed by the smoothing processing means is data between the front and rear lines on which an image is formed, and is provided with a parallel-serial conversion means that converts parallel data into serial data for each of the front and rear lines. is there.

Further, in the image recording apparatus of claim 3, in addition to the configuration of the image recording apparatus of claim 1 or 2, the bus arbitration means is in the storage means side in response to a read request from the image forming means. When the control bus of is separated from the control bus of the central control means and is connected to the image forming means side, the smoothing calculation data is transferred from the storage means side to the image forming means side via the control bus, and in parallel with this. The central control means is adapted to perform processing other than access to the storage means.

[0009]

According to the image recording apparatus having the above structure, the bus arbitration means is located between the control bus on the central control means side and the control bus on the storage means side, and the image forming means issues a read request. At normal times, the control bus on the central control means side and the control bus on the storage means side are connected. As a result, the central control unit controls writing of image data to the storage unit via the control bus. Further, the bus arbitration means arbitrates so that when the image forming means issues a read request, the control bus on the storage means side is disconnected from the control bus on the central control means side and connected to the image forming means side. Thus, the smoothing calculation data can be transferred from the storage means to the image forming means to the smoothing processing means in response to the read request from the image forming means. Then, the image data subjected to the smoothing process is recorded by the image forming means.
Since the control bus of the central control means is disconnected from the control bus of the storage means during smoothing operation data transfer, other processing can be performed in parallel with the operation data transfer. Further, in the image recording apparatus of the second aspect, in addition to the operation of the image recording apparatus of the first aspect, when a read request is issued from the image forming means, image data between lines before and after image formation is stored. The image data, which is read out from the means, is converted into parallel data by the parallel-serial exchange means, and smoothing processing is performed. Further, in the image recording apparatus of claim 3, in addition to the operation of the image recording apparatus of claim 1 (or claim 2), when a read request is issued from the image forming means, the bus arbitration means is set to the storage means side. When the control bus is separated from the control bus of the central control means and connected to the image forming means side, the smoothing calculation data is transferred from the storage means side to the image forming means side via the control bus, and in parallel with this, the central processing is performed. The control means performs processing other than access to the storage means.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a case where the present invention is applied to a facsimile apparatus, and FIG. 2 is a block diagram showing an arbitration circuit 40 of the apparatus. This facsimile machine has a program ROM 10 and a CP as a central control means.
U20, a page memory 30 as a storage means such as a DRAM, and an arbitration circuit 40 as a bus arbitration means for arbitrating the connection between buses.
The CPU 20 and the arbitration circuit 40 are the control bus 5 on the CPU side.
0, and the page memory 30 and the arbitration circuit 40 are connected to each other via a control bus 60 on the page memory side. The control bus 50 is composed of an address bus 50A and a data bus 50D, and the control bus 60 is an address bus 60A and a data bus 60D.
It is composed by. The control bus 70 on the image forming apparatus 90 side, which serves as an image forming unit to be described later, has a data bus 50D and a data bus 6 via the gate array of the arbitration circuit 40.
It is connected to 0D.

The control program necessary for the operation of the CPU 20 is stored in the program ROM 10 in advance. C
The PU 20 receives a clock from a clock circuit (not shown) and generates a system clock φ (see FIG. 3) having a predetermined frequency. The CPU 20 operates in synchronization with each system clock φ according to the control program in the program ROM 10. Also, the CPU 20
Has a WAIT terminal 21 for matching the access speed of the external memory and the input / output circuit.
The terminal 21 is connected to the arbitration circuit 40. When the WAIT terminal 21 is arbitrated by the arbitration circuit 40 and is active, that is, at a low level (see WAIT / signal in FIG. 3), the CPU 20 performs its operation. Stop at the system clock unit. Note that / indicates negative logic.

The page memory 30 has a memory capacity of 1 from the CPU 20.
Image data for pages and control variables are temporarily stored. Since the page memory 30 is composed of a dynamic RAM (hereinafter referred to as DRAM), it needs to be refreshed. This refresh is performed by the arbitration circuit 40 receiving a timer output from the refresh timer 40a. In order to perform smoothing processing on the front and back lines, processing line parallel-serial (P-
An S) data conversion circuit 80 and a front line parallel-serial (P-S) data conversion circuit 85 are provided, and these are connected to the arbitration circuit 40 via a bus 70 on the image forming apparatus 90 side which is a recording unit. .

Each of the PS data conversion circuits 80 and 85 comprises a register for several bytes and a data conversion unit for converting parallel data into serial data. These P-S
The data conversion circuits 80 and 85 sequentially store each parallel data from the arbitration circuit 40 by the register, and
The stored parallel data is sequentially converted into serial data by the data conversion unit and output to the laser scanning image forming apparatus 90 via the smoothing processing circuit 87. The image forming apparatus 90 forms a latent image by scanning a laser beam modulated corresponding to an image in synchronization with a horizontal synchronizing signal (hereinafter referred to as a BD / signal) of the laser beam on a photoconductor. During laser light modulation for image formation, image data is required at a constant speed. The smoothing processing means is composed of both PS data conversion circuits 80 and 85 and a smoothing processing circuit 87.

Next, the arbitration circuit 4 constituting the essential part of the present invention.
An outline of the configuration and the function of 0 will be described with reference to FIG. The arbitration circuit 40 is also called a bus arbiter circuit that plays a role of arbitrating access requests to the page memory 30. The access request includes a data request from the image forming apparatus 90 to the page memory 30, the CPU 2
There are requests for reading and writing control variables from 0 to the page memory 30 and a refresh request for the page memory 30. The arbitration circuit 40 according to the present embodiment is configured such that the CPU 2 normally operates.
The bus on the page memory 30 side is connected to the bus on the page memory 30 side, and when there is a data read request for image recording, the above buses are disconnected and the bus on the page memory 30 side is connected to the image forming side bus. To connect to.

If the CPU 20 is accessing the page memory 30 or refreshing the page memory 30 when the image data is read from the page memory 30 for image recording by the image forming apparatus 90, the arbitration circuit. 40 makes the image data read from the page memory 30 stand by, and immediately after the access or refresh ends, the image data is read from the page memory 30. Also, page memory 3
When trying to refresh 0, the image forming apparatus 9
0 is reading image data from the page memory 30 for image recording, or the page memory 3 of the CPU 20.
If 0 is being accessed, the arbitration circuit 40
The page memory 30 is immediately refreshed after the read or access is completed. Further, when the CPU 20 attempts to access the page memory 30, if the image data is being read from the page memory 30 or the page memory 30 is being refreshed, the arbitration circuit 40.
Applies a WAIT to the CPU 20, temporarily suspends the operation of the CPU 20, and releases the WAIT for the CPU 20 after the image data is read or refreshed. After that, the page memory 30 is accessed again to transfer data from the CPU 20 to the page memory 30.

Next, the configuration and function of the arbitration circuit 40 will be described in more detail with reference to FIGS. 1 and 2. The page memory access arbitration unit 40c, which is a main component of the arbitration circuit 40, includes an access request for the page memory 30 of the CPU 20, an image data read request from the image forming apparatus 90, a refresh request for the page memory 30 of the refresh timer 40a, and the CPU 20. Access to the page memory 30 of the image forming apparatus 90
The completion of reading the image data from the memory and the completion of refreshing the page memory 30, and the recording / reading timing controller 40d, the refresh timing controller 40e, and the CPU access timing controller 40f start recording / reading, refresh control, and CPU access control, respectively. Command start.

In such a case, it is possible to know which timing control unit is operating by monitoring each start command and each completion. Therefore, any one of these start commands can be used to monitor the operating state or request of each timing control unit. Therefore, it is judged as follows. Also, this page memory access arbitration unit 40c
Is displayed during image data reading by the image forming apparatus 90.
When there is an access request from the U20, the CPU 20 waits to stop the operation of the CPU 20 temporarily.
multiply. The address decoder 40j is the CPU 2
It is connected to the 0 address bus 50A and supplies address data to the page memory access arbitration unit 40c.

Such a page memory access arbitration unit 4
The description of the configuration and function of the arbitration circuit 40 will be continued on the premise of the function of 0c. The recording / reading timer 40b is activated in response to the BD / signal in order to output the image data from the BD / signal from the image forming apparatus 90 to the PS data conversion circuits 80 and 85 at a constant speed. It As a result, the recording read timer 40b issues a recording data read request to the page memory access arbitration unit 40c at regular intervals during the period in which the recording data for one line is output. When the page memory access arbitration unit 40c receives the request from the recording and reading timer 40b, the recording and reading timing control unit 40d and the refresh timing control unit 40
If neither e nor the CPU timing control unit 40f is in operation, the same page memory access arbitration unit 40c
The recording / reading timing control unit 40d is instructed to start control, and a bus switching signal is generated. Then, by this bus switching signal, the data bus 60D of the control bus 60 becomes
While being separated from the data bus 50D of the control bus 50, the content of the read address counter 40g is output to the address bus 60A by the recording / reading-CPU address switching unit 40h via the row-column address switching unit 40i.

On the other hand, the recording / reading timing control section 40d.
Is a G for outputting to the page memory 30 in response to a control start command from the page memory access arbitration unit 40c.
RAS1 /, GRAS2 / signal, GCAS1 /, GCA
A row / column address switching timing signal is formed with the S2 / signal and GOE1 /, GOE2 / signal. This allows
The page memory 30 includes a recording / reading timing control unit 40d.
NO in response to GRAS1 /, GRAS2 / signals from
The RAS / signal is output from the R gate 46a, and GCAS1 /, GCAS from the recording / reading timing control unit 40d.
In response to the 2 / signal, the NOR gate 46b outputs the CAS / signal, and in response to the GOE1 /, GOE2 / signals from the recording / reading timing control section 40d, the NOR gate 42c controls the NOR gate 42c. O
The E / signal is output, and the row / column address switching unit 40
i is supplied with a row-column switching timing signal from the recording / reading timing control section 40d through the OR gate 45, and outputs each row and column address to the page memory 30 via the address bus 60A.

The page memory 30 outputs the data of the address designated on the address bus 60A by the arbitration circuit 40 through the data bus 60D. This output data corresponds to GOE1 from the recording / reading timing control unit 40d.
/, GOE2 / signal at the output timing, through the arbitration circuit 40, the bus 70 PS data conversion circuit 8
It is output to 0,85. When the operation of the recording / reading timing control unit 40d ends in this way, the recording / reading timing control unit 40d causes the page memory access arbitration unit 40d to operate.
A recording / reading completion signal is output to c and the read address counter 40g. Therefore, the page memory access arbitration unit 4
0c stops outputting the bus switching signal, while the read address counter 40g sets the address of the data to be read next. When the output of the bus switching signal is stopped as described above, the recording / reading-CPU address switching unit 40
The address bus 60A is connected to the address bus 50A so that h can output the address from the CPU 20, and the gates 43a, 43b, 43c, 43d are responsive to the RD / signal and the WR / signal from the CPU 20.
To connect the data bus 60D to the data bus 50D.

Next, a specific example of the bus arbitration operation in the facsimile apparatus configured as described above will be described with reference to the time chart of FIG. Here, the page memory 30
While the processing line image data B is being transferred from the image forming apparatus 90 to the image forming apparatus 90 (illustrated as a recording unit in the drawing), the address A of the page memory 30 is set so that the image data (decoded data) A is written from the CPU 20 to the page memory 30. The operation when accessed is shown. In this embodiment, C
While the PU 20 is reading code data from the modem, the processing line image data B can be transferred (read) from the page memory 30 to the image forming apparatus 90 in parallel at the same time. Is shown. The image data transfer process is started when the bus switching GBUS signal is output from the page memory access arbitration unit 40c.

Now, from the state where the code data read of the modem and the image data transfer from the page memory 30 to the recording unit 90 are being performed in parallel, the code data read of the former modem is completed and the image data transfer of the latter is completed. A case where the CPU 20 accesses the address A of the page memory 30 in order to write the decoded data A in the page memory 30 in the state where the processing is not completed will be described. In the above image data transfer,
When the image data B at the address B of the page memory 30 is read, the arbitration circuit 40 outputs the RAS / signal and the CAS / signal based on the BD / signal from the image forming apparatus 90 regardless of the contents of the control bus 50. Accordingly, the row and column addresses corresponding to the address B are output to the address bus 60A of the control bus 60, and the data bus 60D is set to the read state (OE / signal). Accordingly, the image data B at the address B of the page memory 30
Is sequentially output to the PS data conversion circuits 85 and 80 as 1-byte parallel data, and the parallel data is sequentially converted to serial data by the PS data conversion circuits 85 and 80 to form an image as a recording signal. It is output to the forming device 90.

During transfer of such image data B, the CP
When the U20 writes the decoded data A to the address A of the page memory 30 by outputting the address A to the address bus 50A of the control bus 50, the arbitration circuit 40
Outputs a WAIT / signal to apply a WAIT to the CPU 20 and stop the operation of the CPU 20. As a result, the completion of the reading of the image data B is waited for the time determined by the system clock unit. In this way, after the reading of the image data B is completed, the arbitration circuit 40 sets the W
By reversing the AIT / signal to high level, the CPU 20
To the RAS / signal, CAS / signal, and WE for each address in the row and column corresponding to the address A already output from the CPU 20 to the address bus 50A.
/ Signal and output again to the address bus 60A. As a result, after the address A is output from the CPU 20, the decoding data A is written to the address A of the page memory 30 after the completion of reading the image data B.

Next, an outline of the operation of the facsimile apparatus as a whole will be described. The CPU 20 writes image data into the page memory 30 through the control bus 50 and the arbitration circuit 40 after the image data is input from an external input device (not shown). Then, under the arbitration operation by the arbitration circuit 40 as described above, the image data in the page memory 30 is sequentially read as parallel data byte by byte in synchronization with each BD / signal from the image forming apparatus 90. It is output and given to each PS data conversion circuit 85, 80. Then, each of the parallel data is taken into the register of each of the PS data conversion circuits 85 and 80, converted by the data conversion unit into serial data, and output to the image forming apparatus 90.
The image forming apparatus 90 sequentially modulates the laser light corresponding to each serial data to form a latent image on the photoconductor, and then forms an image on the photosensitive recording medium. Note that the above-described image data reading is performed at regular intervals during the laser light modulation, but the image data reading may be slightly delayed due to the access to the page memory 30 by the CPU 20 and the refresh of the page memory 30. is there. However, since this delay is absorbed by the registers of the PS data conversion circuits 85 and 80, the output speed of the image data to the image forming apparatus 90 can be maintained constant.

In this embodiment, the smoothing processing circuit 87
Is the previous line PS data conversion circuit 85 and the processing line P.
The smoothing calculation data for the preceding and following lines are input from both of the -S data conversion circuits 80, and smoothing calculation processing is performed. By performing this smoothing calculation process, the outline of the print bitmap data is different before and after performing the smoothing process, and the smoothing process is performed, as shown in FIGS. 4 (a) and 4 (b). As a result, smooth lines are printed out. In the present embodiment, the arbitration circuit 40 separates the control bus 50 on the CPU 20 side from the control bus 60 on the page memory 30 side during data transfer for performing such smoothing processing.
The smoothing operation data transfer can be performed in parallel with the processing of 20, so that high-speed processing can be performed as the entire device.

FIG. 5 is a time chart for showing the operation of the conventional device which does not use the arbitration circuit 40 as in this embodiment, as compared with this embodiment. In the conventional device, since the bus of the page memory is common to the bus of the CPU, as shown in the figure, the code data read of the modem, the image data read, the image data write to the recording unit, and the page memory are performed. Each of the decoded data write of is performed sequentially without being parallel. For this reason, the CPU is in the standby state during the transfer of the smoothing calculation processing between the preceding and following lines in the transfer of the processing line image data, and after the transfer of the smoothing calculation processing is completed, the CPU starts the next processing. Become. Such a standby state has been a factor that hinders high-speed processing. In the present embodiment, such a problem is solved.

As described above, in this embodiment, the access request to the page memory 30 by the CPU 20 and the page memory 30 by the refresh timer 40a are performed.
When at least two requests out of the refresh request and the image data reading request from the image forming apparatus 90 occur at the same time, the arbitration circuit 40 arbitrates the order for satisfying these requests as described above, Since each requirement is satisfied, the image data transfer rate from the page memory 30 required for image formation of the image forming apparatus 90 can be kept constant. In such a case, the control bus 60 is replaced by the control bus 5
The image data is transferred from the page memory 30 to the PS data conversion circuits 85 and 80 separately from the page memory 30 by the CPU 2
Since it is performed by the arbitration circuit 40 instead of 0,
The above-described effects can be further promoted. Further, since the above-described effects are achieved by the arbitration circuit 40 without depending on the expensive line memory, the manufacturing cost of this type of image recording apparatus can be reduced.

Although the page memory 30 is composed of the dynamic RAM in the above embodiment, the page memory 30 may be composed of a static RAM or a pseudo static RAM instead. Further, the arbitration circuit 40 outputs a control signal in response to an access request from the CPU 20 or the like, and when one processing is being performed and another processing request is received,
It suffices to determine the priority order between them in advance, wait for a later request, and after the processing in progress is completed, cancel the waiting and process the request content later. .

[0029]

As described above, according to the image recording apparatus of the present invention, when a read request for image formation is made, the control bus on the storage means side is separated from the control bus on the central control means side to the image forming means side. Since the bus arbitration means arbitrates the control bus so that it is connected, the central control means can perform other processing in parallel while the data transfer of the preceding and following lines is performed in order to perform the smoothed recording. Therefore, as compared with the conventional apparatus using a line memory or the like for performing smoothing recording, the apparatus as a whole can be inexpensive and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an image recording apparatus according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of an arbitration circuit of the device.

FIG. 3 is a time chart showing an arbitration operation of the apparatus.

4A and 4B are diagrams showing image shapes before and after smoothing processing.

FIG. 5 is a time chart showing the operation of the conventional device.

[Explanation of symbols]

 20 CPU 30 page memory 40 arbitration circuit 40c page memory access arbitration unit 50 control bus 60 control bus 70 control bus 80 processing line PS data conversion circuit 85 previous line PS data conversion circuit 87 smoothing processing circuit 90 image formation apparatus

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06T 5/20 G09G 5/28 9471-5G G06F 15/66 405 15/68 410

Claims (3)

[Claims] 1. Storage means for storing image data, smoothing processing means for performing smoothing arithmetic processing on image data read from the storage means in response to a read request, and smoothing processing read out from the storage means by the smoothing processing means. An image forming means for recording the processed image data, a central control means for controlling writing of the image data to the storage means, and a control bus for connecting the central control means and the storage means to each other for signal transmission. In the image recording apparatus, the control bus on the side of the central control unit and the control bus on the side of the storage unit are provided separately, and are provided between these control buses. The control bus of the storage means is connected to the central control hand when the image forming means issues a read request. The image recording apparatus characterized by comprising a bus arbitration means for arbitrating separately from the side control bus to connect to the image forming means side. 2. The image data read from the storage unit in response to a read request from the image forming unit is parallel data, and the image data smoothed by the smoothing processing unit is a line before and after an image is formed. The image recording apparatus according to claim 1, further comprising parallel-serial conversion means for converting parallel data into serial data for each of the preceding and following lines. 3. The storage means side when the bus arbitration means disconnects the control bus on the storage means side from the control bus on the central control means side and connects to the image forming means side in response to a read request from the image forming means. 7. The smoothing calculation data is transferred from the above to the image forming means side through the control bus, and in parallel with this, the central control means performs processing other than access to the storage means. The image recording apparatus according to claim 1 or claim 2.