JPS58116585A - Display indication control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a display display control method, particularly a display display control method in which the contents of an image display memory are repeatedly output and displayed on a display. is divided into multiple blocks that can be accessed independently, and one block on the display
Consideration has been given to transferring the information on the horizontal fins in multiple pieces.

The present invention relates to a display display control system in which the image display memory can be accessed from the processor side and from the display side, respectively, without waiting time.

(Background and problems of uniform technology Conventionally, in display display control methods.

An image display memory is prepared, image information is written from the processor side, and the image information is repeatedly read and displayed from the display side. At this time, the read access from the display side needs to be performed periodically, so that the access from the processor side is placed in a waiting state.
arise. Of course, one memory for the above image display memory
If a cycle is temporarily defined as a processor-side access period and a display-side access period, and each access is performed using each access period, the above-mentioned waiting state does not occur. However, if the memory cycle is set to about 30 on 8, each access to the image display memory must be made at 150 n8, making it impossible to divide the access period as described above.

(Q. Purpose and Structure of the Invention In view of the above-mentioned background, the present invention aims to make it possible to substantially eliminate the above-mentioned waiting time. For this purpose, the display control system of the present invention includes a painter display memory that is accessed at a predetermined period T.

Image information is written from the processor side to the painter display memory, and the 11! Ii In a display display control method in which the image information on the image display memory is read from the display side and displayed on the display, the image display memory is connected to at least two memories.
The memory blocks are divided into blocks so that each memory block can be accessed independently.
The information on the horizontal line is divided into a plurality of information units so that the information on the horizontal line is sequentially read out and supplied from each memory block at the predetermined period T, and from the processor side to the image display memory. The feature is that the access from the display side and the access from the display side are executed in parallel. This will be explained below with reference to the drawings.

(11 Embodiments of the Invention FIG. 1 is an explanatory diagram for explaining the configuration of an embodiment of access to an image display memory according to the present invention, and FIG. 2 is an explanatory diagram for explaining the horizontal axis of an embodiment of access to an image display memory according to the present invention. The explanatory diagram, FIG. 3, shows the configuration of an embodiment of the present invention.

In the case of the present invention, as will be described later with reference to FIG.

The image display memory is composed of at least two memory blocks, and each memory block is configured to be accessible independently and in parallel. And, as shown in Figure 1,
At each memory cycle.

Odd block read, even block read, odd block read from the Disgray side, for example 3QOn8
accessed alternately with a period of

Accesses from the microprocessor (MPU) are synchronized with each other so that an even block write is performed during an odd block read, an odd block write is performed during an even block read, and so on.

In line with this, on the display side,
As shown in FIG. 2, the information on one horizontal scan line 5CAN is divided into information units that can be displayed within 500n8 at the maximum and transferred to the display side. That is, it is ensured that the information corresponding to the information unit is transferred from the two-image display memory to the display side.

Of course, on the display side, it is free to create a buffer for one horizontal line.

By the way, according to the conventional way of thinking, for example, information for one frame is transferred to the display.

Measures have been considered to transfer at least one horizontal scan line's worth of information to the display, and access from a microprocessor (MPU) has had to utilize that free time. Furthermore, access from the microprocessor (MPU) is forcibly allowed, and the display has to be updated midway.

FIG. 5 shows the configuration of an embodiment of the present invention.

1 in the figure is an image display memo IJ, 20.2B is a husband memory block, 30.3g is an address supply multiplexer, 40.4B is a data buffer,
5 represents a multiplexer, 6 a parallel-to-serial conversion circuit, and 7 a data bus.

As described above, by the refresh address from the display (labeled CRT).

In the image display memory 1, as shown in FIG. 1 [cRTJ], memory blocks 20.2E are accessed alternately. For example, at time TO shown in FIG. 1, when the processor side first instructs to perform a paranoid block write, a wait time is waited for synchronization with a memory block read.

Thereafter, write operations are performed sequentially without waiting time.

In other words, it goes without saying that CR from the display side
When T REp kDIL8 is given to the Qi Wei block 20, at the same time the MPU
ADR8 is given to even block 2E. The information successively output from the odd-numbered blocks 20 is transferred to the display side via the parallel-to-serial conversion circuit 6. Meanwhile, data for even block 2E during this period.
Written from bus 7. In addition, the buffers 40 and 4B are
It can be thought of as a buffer that waits for an empty state of the data bus in response to a read from the processor side.

According to the present invention, as described in detail, the information on one horizontal scan line of the display is transferred in pieces, so to speak, but both the display side and the processor side are essentially It can be accessed in no time.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining one embodiment of access to the +m image display memory according to the present invention, FIG. 2 is an explanatory diagram for explaining one embodiment of access to the +m image display memory according to the present invention, and FIG. 1 shows the configuration of an embodiment of the present invention. In the figure, 1 is an image display memory, 2 is a memory block, 3 is an address supply multiplexer, 6 is a parallel serial to p conversion circuit, and 7 is a data bus. Patent applicant Hiroshi Mori (1 other person), agent patent attorney of Fujitsu Ltd.

Claims (1)

[Claims] An image display memory accessed at a predetermined cycle T is provided, and image information is written from the processor side to the image display memory, and the image information on the image display memory is written to the image display memory from the processor side. In a display display control method that reads the information from the display side and displays it on the display. The display memory is divided into at least two memory blocks so that each memory block can be accessed independently, and the information on one horizontal fin on the display is displayed at the predetermined period T. The image display memory is divided into a plurality of information units so as to be sequentially supplied from each memory block, and the image display memory is accessed from the processor side and from the display side. A display control method characterized by being executed in parallel.