JPS6175381A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display device that enables high-speed block transfer to memory and improves responsiveness.

[Conventional technology]

As a conventional image display device, there is, for example, the one shown in FIG.

This image display device has memory processors 2m and 2b connected to a data bus 1, and the image display memory 2 which stores image information to be displayed on ○R block, and the memory processors 2m and 2b, respectively. Multiplex t (M
PX) 3 and 4, a multiplexer 5 that specifies the rounding address for reading information to be displayed from the image display memory 2, and a video signal that converts the parallel signal of the information outputted from the multiplexer 5 into a serial signal. Parallel with /
It is composed of a series (P/8) conversion circuit 6 and more.

The image display memory 2 includes not only memory processors 2a and 2b, but also 7a 2c and 2d for keeping the data slot free in response to reading from the MPU (microprocessor unit) side. is provided.

In the above configuration, the operation will be described below based on the access explanatory diagram shown in FIG. As shown in Figure 4,
In each memory cycle, odd block read, even block read, and odd block read from the display side.
When accesses are performed alternately, such as reads, at a period of 300 ns, for example, the accesses from the MPU take the period from each other, and between odd-numbered block reads (Me block write, and between even-numbered block reads). Corresponding to this process, on the display side, the information on the horizontal scan and line scan is divided into units of information that can be displayed between 30 G and 80 at the maximum. (It is transferred to the display side and processed as C(ru!, uh). That is, it is processed so that it is guaranteed that the information corresponding to the information unit is transferred from the image display memory to the display side.

As mentioned above, by the flare share address from the display, the image display memory 1 is
”, memoripkick 2a.

2b are accessed alternately. For example, at time To shown in FIG. 5, when the processor first instructs to write an even block, it waits for a waiting time to synchronize with the memory block read.
Thereafter, write operations are performed sequentially without waiting time.

That is, if ORT RBF ADBS is given to odd block 2b from the display side, at the same time, MPU ADBS is given to even block 2b from the processor side. The information read from odd-numbered blocks A is transferred to the display side via the P/S conversion circuit 6. Meanwhile, data is written to the even numbered block 2 from the data bus 1 during this time.

[Problem that the invention seeks to solve]

However, in conventional image processing devices, the cycle time of the refresh memory is defined by the timing conditions on the display side (ORT read cycle, etc.), so processing cannot be performed in accordance with the transfer timing conditions on the MPU side. This has the disadvantage of poor responsiveness.

[Means and effects for solving the problems] The present invention has been made in view of the above.

In order to enable high-speed writing and improve responsiveness, refresh memory is divided into multiple blocks that correspond to interlaced scanning fields and can be read and written independently, and blocks other than the block that is currently being displayed are written. The present invention provides an image display device for general use.

〔Example〕

Hereinafter, the image display device according to the present invention will be explained in detail.

FIG. 3 shows an example of an image processing device to which the present invention is applied, including an image input device 10 that optically scans a document, etc. and converts it into a stain signal using COD, etc.; An image memory 11 that temporarily stores image data, an image processor 12 that performs input/output operations, editing (reduction, enlargement, movement, rotation, deletion, etc.) operations, display control, etc. of data in the memory 11, which will be described later). Image processor 1 including display refresh memory, display timing control circuit, etc.
2, an image display device 13 that creates a display signal for image information transferred from the image memory 11 to the display refresh memory; and a file device 14 (magnetic disk, optical disk, etc.) that stores image data input from the image input device 10. and a zero T15 that is driven by a display signal generated by the image display device 13 to display an image.

In the above configuration, image data from the image input device IO is stored in the image memo I711.

This image data is processed by the image processor 12 into an external image processing device, image display device 13 or file device 1.
4, or image editing processing is performed. While image editing processing is being performed by the image processor l2, the image is displayed on the ORT 15 using a display-only refresh memory provided in the image display device 13, and image information is updated every time an image editing operation is performed. is transferred to the refresh memory, and the display information is updated. Preservation of the contents of the image memo +711 can be done by transferring the data in the memo to the 7-isle device. Fig. 1 shows an image display device 1 which is an embodiment of the present invention.
1 field refresher memory 22, which reads the image-display data corresponding to the first field of the interlace through the data bus 21 and stores it;
M27 yield refresh memory 23 that stores image display data corresponding to the second field of the interlace, and addresses of field refresh memories 22 and 23 connected to the address bus 20 to allow the MPU to access non-public fields. Multiplexers 24 and 25 for selecting an address, field reflex/yume 3s 22 and 23, buffer drivers 26 and 27 for reading image information onto a data bus, and an ORT.
A timing generation circuit 28 generates a periodic signal to 15 and a timing signal to each part, and outputs an address designation signal for reading the refresh memory for display operation based on the timing signal of the circuit 28. The display address generation circuit 29 selects the address information of the image processor 12 and the address information of the display address generation circuit 29, refreshes the first or second field, and displays them in order to supply them to the memory. Inverter 3G that switches multiplexers 24 and 25 according to the field
and a multiplexer (■■) 3 that selectively outputs image data from the field reflex memory 22 or 23.
1 and a P/Si conversion circuit 32 for converting parallel image data from the MPX 31 into serial image data.

In the above configuration, the display address generation circuit 29 updates the addresses of the field refresh and memories 22 and 23 using a built-in address counter in response to a timing signal from the timing generation circuit 28. On the other hand, ■
'X 24 and 25 are alternately switched by an address switching signal output from the timing generation circuit 28 in accordance with the display field, and either the field refresh, memory 22 or 23 connected to the selected MPX is displayed. It is connected to the address generation circuit 29, the display field refresh memory is accessed, and the image information at the accessed address is serially converted by the P/3 conversion circuit 32 via the MPX 31.
The image is displayed in 5.

On the other hand, the refresh memory of the non-display field is connected to the corresponding MPX 24 or 25 system bus, so it can be freely accessed from the image processor (!, 12 side). Reading and writing are performed individually by switching alternately.

FIG. 2 shows a memory cycle when the first field refresh memory performs a display operation and the second field refresh memory performs a write operation. As mentioned above, the display cycle is ORT 15
However, according to the present invention, multiple blocks of refresh and memo IJO are selectively used, and the reading time is slower than the writing time to the memory. During field display operation, reading/writing to the second field can be performed continuously at any cycle time.
Reading/writing can be performed without being restricted by the display clock frequency, display memory cycle time, etc. Further, by making the noid cycle time equal to or greater than the cycle time of the acupuncture time, writing operations to other fields can be completed during the display operation, so a display device with good responsiveness can be constructed.

〔Effect of the invention〕

As explained above, according to the image display device of the present invention,
The refresh memory has a capacity multiple times that of the display screen, and is divided into multiple programs that can be read and written independently on a field-by-field basis. Read/write can be performed arbitrarily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing an example of cycle time in the present invention, and FIG. 3 is a block diagram showing an example of an image processing device to which the present invention is applied. , FIG. 4 is a block diagram showing an example of a conventional image display device, and FIG. 5 is a memory cycle diagram of the conventional device. Explanation of symbols 10...Image input device, ll...Image memory, 1
2... Image processor, 13... Image display device, 14... File device, 15... ORT,
20...Address bus, 21...Data bus, 22゜23...Field reflex, memory, 24゜25, 31--Multiplexer (Fl[
)X ), 30...inverter, 32...
P/8 conversion circuit. Figure 1 Figure 3

Claims (1)

[Scope of Claims] An image display device that reads data from a display refresh memory in which image memory data is stored and displays an image by interlaced scanning, wherein the capacity of the refresh memory is multiple times that of the display screen; an image comprising: memory configuration means for dividing the memory block into a plurality of blocks corresponding to fields of interlaced scanning; and memory control means for operating the divided memory blocks as read or write independently on a field-by-field basis. Display device.