JPS59210485A - Video ram controlling circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a video RAM control circuit used in a CRT display device that displays characters, graphics, etc.

[Technical background of the invention and its problems]

In general, dynamic memory used for information storage is more complex to control and slower than static memory. This evening, the dynamic type memory was used as the video RAM (hereinafter referred to as V-RAM) of the CRT display device.
If the number of displayed characters is large, the V-RAM will be occupied only by display access according to the read address from the CRT controller during the character display period, and write and read accesses from the CPU (CPU access) will be treated as display accesses. It will not be possible to run in parallel.

Therefore, in the past, the following V-RAM access means'y
l (was taken.

1) Allow CPU access only to areas where there is no display access during the horizontal or vertical retrace period.

2) Duplicate V-RAM and operate in parallel to always maintain CP
Enable U access.

3) Always give priority to CPU access over display access and enable CPU access each time a request for CPU access occurs.6 However, each of these V-RAM access means:
Each of them had the following inconveniences.

That is, in the V-RAM access means 1), CPU access is limited only to the horizontal and vertical retrace periods, resulting in a decline in the display performance of the device;
- Since the RAM must be duplicated, the cost of the device increases significantly, the configuration becomes complicated, and reliability decreases.

Furthermore, the access means 3) switches from display access to CPU access each time a request for CPU access occurs, resulting in a decrease in display quality.

In this way, in the conventional V-RAM access means,
If display access is given priority in order to improve display quality, CPU access will be restricted and the display performance of the device will deteriorate, and if you try to improve both display performance and display quality, it will be very expensive in terms of cost. Each of them has a major drawback in that the configuration becomes extremely complicated, leading to a decrease in reliability.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is a video RAM that enables the CPU to access the video RAM at all times without deteriorating the display quality with a simple and inexpensive configuration, and that can significantly improve the performance of the display device. The purpose is to provide a control circuit.

[Summary of the invention]

The present invention performs continuous readout of even-numbered characters (multiple characters) at the time of display access to the video RAM, and allocates the time surplus generated by the continuous readout to CPU access during the display period. Always C even in
It enables video RAM access from the PU side and speeds up screen writing and reading.This allows for a simple and inexpensive configuration without duplicating the video RAM, and without deteriorating display quality. The performance of display devices can be improved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing a system configuration in an embodiment of the present invention. In the figure, 100 is a CPU that controls the entire system, and the system bus 1 of this CPU 100 is
A main memory (MEM) 102 , a display control unit (DISP-CTL) 103 , and an Ilo-INTF 104 are connected to the Ilo-INTF. Normally, the CPU 100 uses its own clock generation source (O8
C1) 106, and executes processing operations according to the clock (CPU-CLK) from this clock generation source 106. On the other hand, the display control section 103 also controls the CRT display section (DIS).
P-MNT) Since an operating clock determined from the screen specifications of 105 is required, a unique clock generation source (O8C2) is used.
107, and performs a display operation using the dot clock (DOT-CLK) from this clock generation source 107 as a basic clock.

FIG. 2 is a block diagram showing the configuration of the display control section 103 shown in FIG. 1 above. In the figure, 20 is clock generation source 1
The timing control unit (TIMING) generates various timing signals used for display control using the dot clock (DOT-CLK) from 07 as the basic clock.
-CTL), and in particular, a continuous page read control that makes an even number of characters (for example, two) characters appear when accessing a V-RAM display, and a CPU that utilizes idle time due to this continuous read control, especially according to the present invention. It has the function of generating various signals used for access allocation control, and each of these signals is handled by them. 202 is a video RAM (hereinafter referred to as V-RAM) that stores one screen's worth of display information (character code or dot/mother turn data), where Id, '? It has a dynamic memory element configuration that allows address specification in multiple column addresses (that is, multiple column addresses can be specified on a row address). 203 is a display data buffer (DIS, P-B
UF), 204 is V-RAM 202 (7) Lead/
Read/write data bar for storing write data, 77f
Yes (R/w-BUF). 2θ5 and 206 control synchronization control and video signal output control of the CRT display section 105, 205 is a CRT control section (hereinafter referred to as CRTC), and 206 is a video control section having a character generator (CG), a shift register, etc. Signal output control section (V
IDEO-OUT-CTL). 207 is CRTC
zos YoD generated v-RAM access address (
VAD) and the V-RAM access address (CAD) from the CPU 100, the CPU receives the V-RAM access address (CAD) from the timing control unit 201. According to the contents of the COL signal and the COL signal, each column address is divided into V-
This is an address selector (ADH-8EL) that outputs onto the RAM address line (MAD). 20B is CPU
A wait control unit (WAI) for controlling the timing of V-RAM access with
T-CTL).

3 and 4 are for explaining the operation in one embodiment of the present invention, and FIG. 3 shows the display control unit 10.
FIG. 4 is a timing chart of various signals in FIG. 3. FIG. In Figure 3,
V-RAM 202 t7) 7'-Taha,X (V
-DATA-BUS), there is a bus selection switch (B
US-8EL) is interposed, but this switch (B
The control signal (US-8EL) and control signal (VDS) are for convenience of explanation and do not actually exist, and are actually realized by changing the data flow isometrically by bus interface control. Also, in the figure, RAS, CAS,
COL.

CPUcycle, VDS, ODA, DLD
, CGLD, EN, CPU CAS.

VWT is a signal output from the timing control section 201. Here, m is a row address select signal, 5 is a column address select signal, and 5 is a column designation signal for specifying the row address/column address.
CPUcyqle is a signal indicating the V-RAM access timing of CPU 7 o o, VDS is a signal indicating the V-RAM access timing of CPU 7 o o
' - V-DATA-BUS switching control signal, ODAil: Odd number (ODD) when reading consecutive pages with an even number (for example, two) of characters when accessing the V-RAM display Address/even number (EV
EN) An odd address designation signal for specifying an address, DLD outputs the display read data DRD stored in the display data buffer 203 to the video signal output control unit 206.
CGLD is a load timing signal for generating display and turn data (DPD) from the character generator (CG).
This is a load timing signal for applying display pattern data (DPD) generated by G) to a shift register to obtain a video signal (VIDEO). CPU CAS is C
A signal for latching the read data of the V-RAM 202 into the read data buffer 204R at the time of PU access, and EN is the read data (CHD) stored in the read data buffer 204H at the time of CPU access.
The data of CPU 100 is X (CPU-DATA
-RAS), WILT ld
This is a timing signal for storing write data from the CPU 100 in the write data buffer 204W and supplying it to the V-RAM 202, and is output before and after the CAS signal. WAIT is a wait signal sent from the wait control unit 2013 to the CPtJ 100, and R/W is a wait signal sent to the CPtJ 100.
The read/write signal MRQ sent from U l O θ to the weight tent roll unit 208 is the same memo IJ IJ quest signal.

In addition, the V-RAM address line (MAD) shown in FIG.
Among the above signals, VRA is the row (RO) of the V-RAM 7 addresses (VAD) generated by the CRTC205.
W) Address and VEA are even numbers in the same column (COLUMN
EVEN) address, VOA is an odd number in the same column (COLU)
MN 0DD) address, CRA is the row address of the V-RAM address (CAD) generated by the CPU 100, and CCA is the same column address. Also, CR
V-8YNC, which is output more than TC2θ5, is a vertical synchronization signal, and H.5YNC is a horizontal synchronization signal.

The operation of one embodiment will now be described with reference to FIGS. 1 to 4. The CPU J 00 executes processing operations using the clock (CPU-CLK) generated by the clock generation source 106 as a basic clock, and the display control 1 section 103 uses the clock (DOT-CLK) generated by the clock generation source 1θ7 as a basic clock.
Display control is performed using K) as a basic clock. The timing control section 201 of the display control section 103 receives the dot clock (DOT-CLK) from the clock generation source 107.
) and generates various timing signals to control display timing. During normal display access, the address selector 207 is generated more often than the CRTe 205.
-Select all RAM access addresses (vAD) and transfer this address data to the V-RAM address line (MAD)
Also, the bus selector switch (B″US-8EL
) performs bus switching so that the V-RAM 202 (D read Lf-1 is sent to the display data buffer 2θ3,
(7) Read data from the V-RAM 202 according to the display V-RAM access address (VAD) from the CRTC 205 is sent to the video signal output control unit 206 via the display data buffer 203, and a dot serial video signal (VIDEO ) is converted to This video signal (V
IDEO) is sent to the CRT display section 105.

Here, V-RAM? 0,? Specific operations during display access and CPU access will be described with reference to FIGS. 3 and 4. When accessing display data,
The timing control section 20 controls RAS, CAS, and COL at the timing shown in FIG.

Each signal such as ODA is output, and continuous page reading is performed during two character times. That is, this continuous page reading is performed by issuing two CAS and one ODA for one RAS. This page readout is executed at high speed even though the addresses are consecutive, and two characters are read out within a time period of 10 dots. At this time, since the two-character time is the time for 16 dots, there is a vacant time (TB) for 6 dots. Here, using this free time (TB), CPU Z
00 to access the V-RAM 202,
When there is an access request from the CPU 1θθ to the V-RAM 2θ2, a CPU access timing is inserted into this free space (TB). That is, when the MRQ signal from the CPU 100 is input to the weight control section 208 at the timing shown in FIG.
waits until the CPU access can be executed, and adjusts the timing difference between the CPU iθO and the CRTC 205. Then, when the timing is right, the CPU cy from the timing control section 201
The address selector 207 and the path changeover switch (BUS-8EL) are switched by the CLE and VDS signals, and the address selector 207 switches from the CRTC 205 to the V-RAM 7 access address (VAD) to the CPU J o. Select the V-RAM access address (CAD) from o and press the path changeover switch (BUS-8E
L) is V-RAM202 (7) f - Tahas (V-D
ATA-BUS) read/write data buffer 20
Switch to side 4. During this CPU access, the CPU
When the U 100 writes f'-cod to the V-RAM 202, the C data stored in the write data buffer 204W is
The write data from PU 100 is synchronized with the surface signal,
V-R via path changeover switch (BUS-8IliL)
AM 202. Also, CPU100 is VR
When reading AM 202 data, V-RAM 2
02 (After the D read data is stored in the serial read data buffer 204H by the CPU CAS signal, it is output onto the CPU data bus by the EN signal. The signal on the V-RAM address line (MAD) during the above operation With the timing shown in FIG.
't, 's) -VOA (VAD Tukaram odd address) -CRA (CAD row address) -C
CA (CADO column address).

Also, when the CPU is not accessing, data at even addresses and data at odd addresses read from V-RAM 202 are as follows:
The trailing edge of the CAS signal is alternately stored in the display data buffer 203. The read data at even and odd addresses are stored in the continuous read display data buffer 203 for different periods of time, and are not displayed at this timing. Therefore, the display data stored in the display data buffer 203 is fetched into the video signal output control section 206 and re-held in the video signal output control section 206 using a DLD signal at regular intervals synchronized with the display operation to display the characters! (However, this is not necessary in the case of graphic display) and is further loaded into a shift register by the CGLD signal, and then output as a dot serial video signal (VIDEO).

Incidentally, in the above embodiment, I CP during the 2 character period
Although a U cycle is inserted, if the display speed is faster and it is not possible to insert a CPU cycle in a 2 character period, the display data buffer (DISP- BUF
) can be easily finite.

〔Effect of the invention〕

As detailed above, according to the video RAM control circuit of the present invention, the performance of the display device is greatly improved by allowing the CPU to access the video RAM at all times without deteriorating the display quality with a simple and inexpensive configuration. can be done.

[Brief explanation of the drawing]

1 to 3 are block diagrams showing the configuration of one embodiment of the present invention, FIG. 4 is a time chart for explaining the operation of the above embodiment, and FIG. 5 is another embodiment of the present invention. It is a time chart for explaining. 100...CPU, 103...Display control unit, 105
. . . CRT display section, 106, 107 . . . Clock generation source, 201 . . . Timing control section, 202
...Video RAM (V-RAM), 203...Display data buffer, 204...Read/write data buffer, 205...CRT control section (CRT
C), 206... video signal output control section, 207...
-Address selector, 208...wait control section. Applicant's agent Patent attorney Takehiko Suzue 535

Claims (1)

[Claims] A video RAM that stores display information consisting of character codes or doratono and turn data, and this video RAM.
In order to read out the display information from AM, this video R
A circuit that successively accesses an even number of memory locations in AM and continuously reads an even number of the display information, and this read circuit sequentially holds the display information that is successively read from the video RAM. a buffer storage circuit that stores the display information held in the buffer storage circuit;
A circuit that converts into a display signal according to display timing, and C
means for making access to the video RAM from the PU wait until a free time created by the difference between the time required to read display information in units of the even number and the time required to display the even number of display information; A video RAM control circuit comprising: a circuit that supplies a video RAM access address from the CPU to the video RAM when time is detected, and reads and writes the display information to the video RAM.