JPS6323191A - Graphic display unit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a graphic display device, and particularly to a graphic display device suitable for speeding up multi-window display processing.

[Conventional technology]

In recent years, systems with built-in dedicated hardware to display multi-window displays at high speed have spread to office automation workstations and personal computers. Execute window display using the rask calculation function that transfers rectangular area memory at high speed. These dedicated hardware are separated from the host processor and placed in a graphics display device, which is equipped with a bitmap display, capable of multi-window display, and can display Kanji characters as graphics. And to perform these graphics displays at high speed.

Graphic display devices are equipped with hardware for rask calculations that has the function of specifying a rectangular area in display memory such as a frame buffer bit by bit and transferring it to another display location. Perform multi-window control. An example of a display device that supports a multi-window function by hardware is disclosed in Japanese Patent Application Laid-Open No. 116692/1983.

[Problem that the invention seeks to solve]

In the conventional example above, when supporting the multi-window function with hardware, the display priority between windows is not considered, and when a window is moved or the window display priority is changed, the frame buffer is rewritten. , there was a problem in that it took a long time to display the change window.

The purpose of the present invention is to solve such conventional problems, and even when a window is moved or the window display priority is changed, multi-window display can be performed instantly, and the position, size, and distance between windows can be changed. An object of the present invention is to provide a graphic display device that can speed up window operations such as changing display priorities.

[Means for solving problems]

In order to solve the above problems, in the present invention, the dot data stored in the frame buffer is read out and displayed on the monitor, and one or more dot data in the frame buffer is displayed at one or more arbitrary monitor locations. The location of the segment in the frame buffer and the display position on the monitor when displaying multiple segments in the frame buffer in a graphics display device that performs multi-window display and is mapped 1:1 from the segment indicating the part of .

A display control table that stores parameters related to display quality between segments, a display control processor that operates according to the display control table, and reading of a frame buffer related to display on a monitor under the control of the display control processor. The present invention is characterized in that display control means for generating addresses is provided, and when displaying a plurality of segments in the frame buffer, display priority is determined between the segments.

[Operation] The present invention provides hardware for a multi-window function by a display control means controlled by a display control processor that operates according to a display control table that sets the positions and sizes of multiple windows and display priorities among windows. support is now possible. Therefore, by rewriting the display control table from the upper processor,
Window operations such as changing the window position, size, and display priority between windows can be performed instantly.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a graphic display device showing one embodiment of the present invention.

In FIG. 1, 1 is a host processor that rewrites display control parameters in RAM 3, 2 is a display control processor that controls display control means 5, and 3 is a frame for displaying a plurality of segments in frame buffer 7. RA that stores parameters related to the location of segments in the buffer, display position on the monitor, and display quality between windows
M, 4 is a display synchronization signal generation circuit that generates a vertical/horizontal synchronization timing signal in order to synchronize the display; 5 is a frame buffer 7 readout related to display on the monitor 9 under the control of the display control processor 2; 6 is a display control means for generating addresses; 6 is a drawing control means for controlling access to the frame buffer 7 from the host processor 1; 7 is a frame buffer in which tod data is stored; 8 is a video controller for converting dot data into video data. Conversion circuit, 9 is a monitor for multi-window display, 10-1 to 1° are registers, 11-1 to lO are counters, 12-1 to 1o are registers, 13-1 to 1o are registers, 14-1 to 10
15 is a conveyor circuit that compares the counter output and register output; 15 is a multiplexer (hereinafter referred to as MPX) that selects one output from a plurality of inputs; 16 is a counter/MPX control circuit that controls the counter and MPX 15;
A write/read control circuit 17 controls writing/reading of dot data to/from the frame buffer.

In this embodiment, five windows can be displayed simultaneously, and display priorities among the windows can be arbitrarily determined.

Upper processor l and display control processor 2 in Fig. 1
The more accessible RAM 3 has the format shown in FIG. WISA to W5SA), the horizontal size of the segment in the frame buffer 7 corresponding to the window (
WI 5H5-W55H3), horizontal display position (W
IHP-W58P), vertical display position (W I V P-W5 V P) to specify the vertical position, horizontal display width (WI HW) to specify the horizontal display width of the window
-W5HW), vertical display width (wl VW-W5VW) that specifies the vertical display width, and display priority (W5HW) that specifies the display priority when windows overlap
Each display control parameter of IPR-W5PR) is stored. Furthermore, a work area for the display control processor 2 to operate is also secured. These display control parameters are set by the upper processor l to determine the display positions of the windows and the display priorities among the windows.

The display control processor 2 operates based on the display control parameters and receives the vertical/
According to the horizontal synchronization timing, the display control parameters in RAMa are read in the vertical retrace interval of the monitor 9, and the display start address and display end address on the frame buffer of each window are calculated in the horizontal display order in all rasters of the display, Store in the work area of RAM3. At this point, the display priority between windows, that is, W in FIG.
IPR-W5PR is reflected in the display start address and display/display end address calculated by the display control processor 2 and stored in the work area of the RAM 3.

For example, FIG. 3 shows an example in which four windows are displayed on the monitor 9. The position of each window in the frame buffer 7 is shown in FIG.
The above display format is shown in FIG. 3(b), and the display information in the raster i in the RAM 3 work area calculated by the display control processor 2 in the vertical retrace interval of the monitor 9 is shown in FIG. 3(c). Raster i is displayed in window 1
→ Window 2 → Window 3 - Window 4 → Window l The 0 display control processor 2 should perform the following steps:
WIDSAI to WLDSA2 are stored in registers 10-1 to 5, which are 10 each for the horizontal display section of raster i-1 and the horizontal retrace section of raster i, and WIDSAI to WLDSA2 are set in registers 12-1 to 5.
WIDEA1 to WIDEA2 are set in sequence. In addition,
Add all F to the redundant registers 10-6 to 10.
Further, all F's are set in registers 12-6 to 12-10.

When the horizontal display interval of raster i begins, register 10
-1~10→Counter 11-1~10. register 1
The contents are transferred from registers 1-1 to 10 to registers 12-1 to 12-10.

The counter/MPX control circuit 16 controls the counter 11-
A clock having the same frequency as the memory cycle of the frame buffer 7 is supplied to the counter 11-1, and the counter 11-1 counts up by 1 for each memory cycle.
Under the control of the counter/MPX control circuit 16, the data of the counter 11-1 is supplied to the address line of the frame buffer 7. In this way, the counter 11-1 counts up according to the display on the window 1 on the monitor 9, and when the display on the window 1 ends, the values of the counter 11-1 and the register 13-1 become the same, and this state The conveyor circuit 14-1 detects this and notifies the counter/MPX control circuit 16 of the detection information. When the counter/MPX control circuit 16 receives this detection information, it stops supplying the clock to the counter 11-1 and starts supplying the clock to the primary counter 11-2. The MPX 15 is controlled so that the data is supplied to the address line of the frame buffer 7. That is, the display of window 2 will start on monitor 9.

Thereafter, the display of window 1→window 2→window 3→window 4→window 1 will be performed on the monitor 9 in the same manner.

In the above procedure, the display address is supplied to the frame buffer 7 by the display control processor 2 and the display control means 5,
The dot data read out from the frame buffer 7 is converted into video data by the video conversion circuit 8, and a desired display is performed on the monitor 9.

Furthermore, when dot data is accessed from the upper processor 1 to the frame buffer 7, the write/read control circuit 17 issues an access request to the counter/MPX control circuit 16, and the 1MPX 15 is accessed by the output of the write/read control circuit 16. The counter/MPX control circuit 16 is controlled so that the address is supplied to the address of the frame buffer 7.

Note that the display synchronization signal generation circuit 4 supplies the vertical/horizontal synchronization signal to the monitor 9, and also notifies the display control processor 2 of the vertical/horizontal blanking interval and the counter/MPX control circuit 15 of the horizontal display interval. .

In this embodiment, a display control processor is used to determine the display quality between windows (segments), but in place of the display control processor 2, a dedicated hardware is used that reads out the display control table and controls the display control means. In addition, in this embodiment, the display control means has 10 registers, counters, etc. in 5, but it is not limited to this. It may be changed as appropriate depending on the number of .

〔Effect of the invention〕

As explained above, according to the present invention, since the multi-window function is completely supported by hardware,
Even when moving windows or changing the display priority of windows, multi-window display can be performed instantly, speeding up window operations such as changing window positions, sizes, and display priorities between windows. can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a graphic display device showing one embodiment of the present invention, FIG. 2 is a diagram showing the format of the contents in RAM 3 of FIG. 1, and FIG. 3 is an example of displaying four windows on a monitor. FIG. 1: Upper processor, 2: Display control processor. 3: RAM, 4: Display synchronization signal generation circuit, 5: Display control means, 6: Drawing control means, 7: Frame buffer, 8:
Video conversion circuit, 9: Monitor, l〇-1 to 10: Register, 11-1 to lO: Counter, 12-1 to 10: L/
Jis'2.13-1~10: Register, 14-1~10
: Conveyor circuit, 15: MPX, 16: Color: /Yu/M
PX control circuit, 17: write/read control circuit. Figure 3 (a+ ~) M3
Diagram (C)

Claims (1)

[Claims] 1. The dot data stored in the frame buffer is read out and displayed on the monitor, 1:1 from segments representing one or more parts in the frame buffer to one or more arbitrary monitor locations. In a graphic display device that is mapped and performs multi-window display, when displaying multiple segments in the frame buffer, the location of the segments in the frame buffer, the display position on the monitor, parameters related to the display quality between segments, etc. A display control table that stores parameters related to multi-window display, a display control processor that operates according to the display control table, and read addresses of frame buffers related to display on the monitor under the control of the display control processor. 1. A graphic display device, comprising: a display control means for generating a display, and determining display priority between segments when displaying a plurality of segments in the frame buffer.