JPH04195355A - Direct memory access device - Google Patents

Abstract

PURPOSE:To facilitate the scrolling of image data by assigning continuous address indirectly to discontinuous address even for a large amount of data which are arranged in discontinuous addresses. CONSTITUTION:When the addresses of transfer sources are arranged discontinuously, the addresses of the transfer sources are defined as continuous data on a memory device and its head address is defined in a source address counter 11. Namely, the continuous addresses of the transfer sources as 1st address information generated by the source address counter 11 are converted into actual discontinuous transfer source address data as 2nd address information by the memory device 12. Consequently, data can be moved at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a direct memory access device that allows automatic transfer of complex data.

Prior Art FIG. 6 is a block diagram of a conventional direct memory access device. In FIG. 6, a source address counter 1 and a destination address counter 2 constitute a set of pointer address generation means, a source address counter 1 generates a transfer source address for automatic data transfer, and a destination address Counter 2 generates a transfer destination address for automatic data transfer.

The addresses generated from source address counter 1 and destination address counter 2 are transferred to address bus 3.
Output to. A memory device 4 as a storage means and a peripheral device 5 are selected by an address bus 3, and a data bus 6 connects input and output of the memory device 4 and peripheral device 5. A data holding device 7 serving as temporary storage means temporarily stores output data from the memory device 4 or the peripheral device 5 to the data bus 6.

The operation of the above configuration will be explained below. First, the memory device 4 or peripheral device 5 is selected through the address bus 3 using an address generated by the source address counter l, and its output data is outputted to the data bus 6. The data output to the data bus 6 is temporarily held in the data holding device 7.

Next, the address generated by the address counter 2 selects the memory device 4 or the peripheral device 5 through the address bus 3, and outputs the data temporarily held in the data holding device 7 to it through the data bus 6.

These operations are performed continuously by incrementing, decrementing, or fixing the source address counter 1 and incrementing, decrementing, or fixing the destination address counter 2, thereby realizing automatic transfer of a large amount of data. In this way, for example, an automatic transfer between the memory device 4 and another memory device, an automatic transfer within the memory device 4 itself or an automatic transfer between the memory device 4 and the peripheral device 5 takes place.

Problem to be Solved by the Invention However, in the above conventional configuration, the data transfer source and transfer destination must be continuous addresses or fixed.
It is not possible to move a large amount of data located at non-consecutive addresses at high speed according to the format, for example,
It has been difficult to scroll image data, which requires moving a large amount of data located at non-consecutive addresses at high speed according to the format.

The present invention solves the above conventional problems by providing direct memory access that allows data to be moved at high speed even if a large amount of data is located at non-contiguous addresses, and thereby enables easy scrolling of image data. The purpose is to provide a device.

Means for Solving the Problems In order to solve the above problems, a direct memory access device of the present invention includes a pair of pointer address generation means for outputting a transfer source address and a transfer destination address, and a pointer address generation means for specifying a transfer source address and a transfer destination address. storage means for reading and writing specific data based on first address information and second address information; and storage means for temporarily storing the data read from the storage means, and storing the data in the storage means when writing to the storage means. The device includes temporary storage means for outputting data, and real address generation means for outputting the second address information to the storage means by inputting address data among the data read from the storage means.

Operation With the above configuration, specific data is read out by the storage means based on the first address information specified by the pointer address generation means, and the second data is read from the real address generation means, which inputs the address data among the specific data, to the storage means. The storage means outputs address information, reads specific data based on the second address information, and stores the specific data read based on the first or second address information in the first or second memory via the temporary storage means. Since the data is automatically transferred by writing to the storage means based on the address information of the transfer source or transfer destination or the transfer source and transfer destination, even if the address information of the transfer source or transfer destination or the transfer source and transfer destination is located in a non-contiguous manner, even if the address information is a large amount of data that is arranged in a non-contiguous manner, it is possible to determine whether the address is a continuous address or a non-consecutive address. can be addressed indirectly, and non-sequential addresses can be processed as well as continuous addresses, allowing data to be moved at high speed, thereby facilitating the scrolling of, for example, image data.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. It should be noted that the same reference numerals are given to those having the same functions and effects as those of the conventional example, and the explanation thereof will be omitted.

FIG. 1 is a block diagram of a direct memory access device according to a first embodiment of the present invention. In FIG. 1, a source address holding device 14 holds the address generated by the source address counter 11 as the actual transfer source address through the data bus 6, and the output data of the memory device 12 or peripheral device 13 selected through the address bus 3.
has been established.

The operation of the above configuration will be explained below. If the transfer source addresses are arranged non-contiguously, first define the transfer source addresses as continuous data in the memory device 12, and then set the first address to the source address counter 11.
Define. That is, the configuration is such that the continuous address of the transfer source as the first address information generated from the source address counter 11 is converted into discontinuous actual transfer source address data as the second address information by the memory device 12. Then, the address data output from the memory device 12 selected by the address generated from the source address counter 11 is transferred and held as an actual transfer source address to the source address holding device 14, and the source address holding device 14 generates the address data. The data of the memory device 12 or peripheral device 13 selected by the address is temporarily held in the data bus holding device 7 through the data bus 6.

Next, the address generated by the destination address counter 2 is sent to the memory device 12 via the address bus 3.
Alternatively, the peripheral device 13 is selected and the data temporarily held in the data bus holding device 7 is outputted to it through the data bus 6.

These operations are performed continuously by incrementing or decrementing the source address counter 11 and incrementing or decrementing the destination address counter 2, or by incrementing or decrementing the destination address counter 2, thereby realizing automatic transfer of a large amount of data.

FIG. 2 is a block diagram of a direct memory access device according to a second embodiment of the present invention. In FIG. 2, an address generated by a destination address counter 21 is selected by a memory device 2 through an address node 3.
A destination address holding device 24 is provided for holding output data from the peripheral device 2 or the peripheral device 23 through the data bus 6 as an actual transfer destination address.

The operation of the above configuration will be explained below. When the transfer destination data is arranged at non-contiguous addresses, first, the transfer destination addresses are defined in the memory device 22 as continuous data, and the start address thereof is defined in the destination address counter 21. That is, the continuous addresses of the transfer destination as the first address information generated from the destination address counter 21 are transferred to the memory device 1.
2, it is configured to convert into discontinuous actual transfer destination address data as second address information. Then, the data of the memory device 22 or peripheral device 23 selected by the address generated from the source address counter 1 is temporarily held in the data bus holding device 7 through the data bus 6.

Next, the address data output from the memory device 22 selected by the address generated from the destination address counter 21 is transferred and held as an actual transfer destination address to the destination address holding device 24. 24 or the memory device 2 through the address bus 3.
2 or the peripheral device 23, and outputs the data temporarily held in the data bus holding device 7 to it through the data bus 6.

These operations are performed continuously by incrementing, decrementing, or fixing the source address counter 1 and incrementing or decrementing the destination address counter 21, thereby realizing automatic transfer of a large amount of complicated data.

FIG. 3 is a block diagram of a direct memory access device according to a third embodiment of the present invention. In FIG. 3, a source address holding device 34 holds the address generated by the source address counter 31 as the actual transfer source address through the data bus 6, and the output data of the memory device 32 or peripheral device 33 selected through the address bus 3.
A destination address holding device 36 is provided which holds the output data of the memory device 32 or peripheral device 33 selected through the address bus 3 as an actual transfer destination address through the data bus 6, using the address generated by the destination address counter 35. ing.

The operation of the above configuration will be explained below. If both the transfer source and transfer destination addresses are arranged non-contiguously, first define the transfer source address and transfer destination address as continuous data in the memory device 32, and then use the first address as continuous data. and destination address counter 35, respectively. The source address holding device 34 (
= memory device 32 that is transferred and held and selected by the address generated by this source address holding device 34
Alternatively, the data of the peripheral device 33 is temporarily held in the data bus holding device 7 through the data bus 6.

Next, the address data output from the memory device 32 selected by the address generated by the destination address counter 35 is transferred and held as an actual transfer destination address to the destination address holding device 36. 36 or the memory device 3 through the address bus 3.
2 or the peripheral device 33, and outputs the data temporarily held in the data bus holding device 7 to it through the data bus 6.

By sequentially performing these operations by incrementing or decrementing the source address counter 31 and incrementing or decrementing the destination address counter 35, automatic transfer of a large amount of complicated data is realized.

In addition, a source address switching device (not shown) that switches between the address output by the source address counter 31 and the address output by the source address holding device 34 to be used as a transfer source address, and a destination address counter. By providing a destination address switching device (not shown) for switching between using the address outputted by 35 and the address outputted by destination address holding device 36 as a transfer destination address, the conventional example can be improved. Thus, it is possible to obtain a direct memory access device that can switch between the device and the devices of the first to third embodiments.

FIG. 4 is a block diagram of a direct memory access device according to a fourth embodiment of the present invention. In FIG. 4, by providing a plurality of source address holding devices 41 and a plurality of destination address holding devices 42, direct memory access using more complicated indirect addressing becomes possible.

FIG. 5 is a block diagram of a direct memory access device according to a fifth embodiment of the present invention. In FIG. 5, two source address counters 51, 52 and two destination address counters 53, 54 are provided.

With the above configuration, when the transfer source addresses are arranged non-contiguously, first, the transfer source addresses are defined in the memory device 55 as continuous data, and the first address thereof is defined in the source address counter 51.

Next, the address of the source address counter 52 is defined in the destination address counter 53, and the first direct memory access is performed. Subsequently, the ratio data of the memory device 55 or peripheral device 56 selected by the address output from the source address counter 52 is temporarily held in the data holding device 7 via the data bus 6, and the ratio data of the memory device 55 or peripheral device 56 selected by the address output from the source address counter 52 is temporarily held in the data holding device 7. The data in the memory device 55 or peripheral device 56 (=data holding device 7) selected by the memory device 55 or peripheral device 56 is outputted via the data bus 6.

Also, if the data at the transfer destination is located at non-contiguous addresses, or even if both the source and destination are located at non-contiguous addresses, this can be easily achieved by performing the same operation. . Furthermore, the source address counter 5
I, 52, destination address counter 53.
54 can be individually incremented, decremented, or fixed to realize more complex direct memory access.

Effects of the Invention As described above, according to the present invention, even if a large amount of data is placed at non-consecutive addresses, consecutive addresses are indirectly addressed to non-consecutive addresses. Since addresses can be processed and data can be moved at high speed, scrolling of image data, for example, can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a direct memory access device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a direct memory access device according to a second embodiment of the present invention, and FIG. 3 is a block diagram of a direct memory access device according to a second embodiment of the present invention. 3 is a block diagram of a direct memory access device according to a fourth embodiment of the present invention, FIG. 4 is a block diagram of a direct memory access device according to a fourth embodiment of the present invention, and FIG. 5 is a block diagram of a direct memory access device according to a fifth embodiment of the present invention. Device Block Diagram FIG. 6 is a block diagram of a conventional direct memory access device. 1.11.31.51.52... Source address counter, 2.21.35.53.54... Destination address counter, 3... Address bus, 6.
...Data bus, 7...Data holding device, 12.22
．． 32.55...Memory device, 13.23.33.5
6... Peripheral device, 14.34.41... Source address holding device, 24.36.42... Destination address holding device.

Claims (1)

[Claims] 1. A set of pointer address generation means for outputting a transfer source address and a transfer destination address, and a storage means for reading and writing specific data based on first address information and second address information specified by the pointer address generation means. temporary storage means for temporarily storing data read from the storage means and outputting the stored data to the storage means when writing to the storage means; and temporary storage means for storing address data among the data read from the storage means. and real address generation means for outputting the second address information to the storage means as an input.