JPH03164850A - Direct memory access device - Google Patents

Abstract

PURPOSE:To perform an optimum operation of an external device by analyzing data read out in a source cycle and generating a status corresponding to this data and reporting it to the external device. CONSTITUTION:A status generator 7 is provided which analyzes contents of a data register 6 to generate a status corresponding to analysis contents and reports it to first and second external devices 8 and 9. When first data D in an address (k) is the pointer to raster data, the status generator 7 outputs a raster ID as a status signal SS. This raster ID is continuously outputted till conversion of the classification of data. While the raster ID is continuously outputted as the status signal SS, first and second external devices 8 and 9 perform the optimum operation corresponding to the raster ID. Thus, the data attribute in an access cycle can be outputted as a signal for the purpose of optimizing the operation of an external storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to
The present invention relates to a direct memory access device that transfers data between a memory device and an input/output device.

[Conventional technology]

FIG. 3 shows an example of the configuration of a data processing device using a conventional direct memory access device (hereinafter abbreviated as a DMA device). In this data processing device,
CPU (Central Processing Unit) 21.
Memory device 22.23. An input/output device 24 and the like are connected thereto, and a DMA device 25 is further connected thereto. Data transfer methods for the data processing device shown in FIG. 3 include a method of transferring data according to a program via the CPU 21, and a method of direct transfer using hardware using the DMA device 25 without using the CPU 21, that is, the DMA method. be.

FIG. 4 shows an example of the configuration of a conventional DMA device 25. As shown in FIG.

The outputs of the source address generator 1 which generates the transfer source address A and the destination address generator 2 which generates the transfer destination address An are supplied to the address switch 3, and based on the output from the timing controller 4, The address switch 3 selectively outputs the data to the system bus 5.

In this conventional DMA device 25 (see FIG. 3), for example, from the memory device 22 to the memory group! 23 by the DMA method, first switch the address switch 4 to the source address generator 1 side, specify the address of the memory device 22 with the source address generator 1, and transfer the data D of the memory device 22. Read the data and temporarily store it in the data register 6, then switch the address switch 4 to the destination address generator 2 side, read the data D in the data register 6, and store it in the memory specified by the destination address generator 2. Write to the address of device 23. As a result, DMA transfer of data D is executed.

[Problem to be solved by the invention]

For normal memory access operations, the conventional DM described above
No particular problem occurs with device A. However, a problem arises when it is desired to change the external storage device or the like to be accessed depending on the content of the access.

For example, in a document processing device that uses cache memory, the cache memory is divided into a low-speed, large-capacity image cache memory that stores large amounts of data such as raster data but is infrequently used, and a low-speed, large-capacity image cache memory that stores other data such as character data and instructions. Some attempts have been made to improve the processing speed of document processing devices by separating the document processing device into a general cache memory that stores data that has a small capacity but is frequently used.

In such cases, conventional DMA devices cannot apply DMA because there is no way to distinguish between access destinations.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DMA device that can output data attributes during an access cycle as a signal in order to optimize the operation of an external storage device.

[Means to solve the problem]

In order to achieve the above object, the direct memory access device of the present invention reads data from a first external device based on an address from a source address generator, temporarily stores it in a data register, and reads out the contents of the data register. A direct memory access device that writes data to a second external device based on an address from a destination address generator, analyzes the contents of the data register, and generates a status according to the analysis contents. Said 1st. The present invention is characterized by providing a status generator that notifies the second external device.

〔Example〕

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, features of the present invention will be specifically described based on examples with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the DMA device of the present invention. Incidentally, the same reference numerals are given to parts and the like that correspond to those of the conventional DMA device shown in FIG.

In this embodiment, in addition to the configuration of the conventional DMA device shown in FIG. 1 and FIG.
Further, first and second external devices 8.9 are connected to the system bus 5. The operation of the DMA device shown in FIG. 1 will be explained below.

The operation of a DMA device includes a source cycle and a destination cycle. A source cycle is a cycle for reading data from a transfer source, and a destination cycle is a cycle for writing data read in a source cycle to a transfer destination. On the right, a series of operations always begins with a source cycle.

First, in the source cycle, it operates to obtain data from the first external device 8. That is, the timing controller 4 controls the source address generator 1, and causes the source address generator 1 to output the source address A to the system bus 5 through the address switch 3. At the same time, the timing controller 4 sends a control signal R/W to the system bus 5 requesting the first external device to read data.
Output.

The first external device 8 receives these signals from the system bus 5 and outputs data D to the system bus 5. The data register 6 temporarily stores this data D. At the same time, the status generator 7 analyzes the data D and outputs the data attributes during the access cycle.

Now, as shown in FIG. 2, if the first data D at address k is a pointer to raster data, the status generator 7 outputs the raster ID as the status signal SS. This raster ID continues to be output until the data type is changed. Note that here, the types of data include raster data representing image information, and general data representing other character data, commands, and the like. While the raster ID continues to be output as the status signal Ss, the first . The second external device 8.9 performs an optimal operation corresponding to the raster ID.

Furthermore, if the data D stored in the data register 6 is a pointer to a raster as described above, the data D is not sent to the system bus 5 but to the source address generator 1. As a result, the source addresses are raster data A, B, and C.

...This is the start address of the area in which it is stored, that is, address 1. And timing controller 4
performs the source cycle operation again from this new address.

In the next source cycle, the raster data is read out in the same order as when the raster pointer was read out and stored in the data register 6. In this case, the status generator 7 notifies the timing controller 4 that the read data is just data. Therefore, the timing controller 4 operates to generate a destination cycle. That is, the timing controller 4 outputs the destination address 80 from the destination address generator 2 to the system path 5 through the address switch 3, controls writing to the second external device 9, and writes the contents of the data register 6.

By repeating this source cycle and destination cycle, the address of the first external device 8 is changed to 1+1 address,!
Data transfer is performed while incrementing the address by +2. When a return pointer is detected at address m-1, the source address is changed to the address where the next raster data pointer is stored, that is, address k+1.

This cycle continues until a new raster pointer or other control code is given to the data register 6.

In addition, in the above-mentioned embodiment, the case where raster data is transferred was explained as an example, but the present invention is not limited to this, and the present invention can also be applied to other data, such as audio data. be able to.

〔Effect of the invention〕

As described above, according to the present invention, when transferring data using the DMA method, the data read in the source cycle is analyzed, a status corresponding to the data is generated, and an external device is notified of this. This allows the external device to perform optimal operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a DMA device according to an embodiment of the present invention;
Fig. 2 is an explanatory diagram showing an example of the structure of raster data, Fig. 3 is a block diagram for explaining general data transfer using the DMA method, and Fig. 4 is a block diagram showing an example of the configuration of a conventional DMA device. be. 1: Source address generator 2: Destination address generator 3; Address switch 4: Timing controller 5 system bus 6: Data register, distaff: Status generator 8: First external device 9: Second external device

Claims (1)

[Claims] 1. Read data from the first external device based on the address from the source address generator and temporarily store it in a data register, read the contents of the data register, and read the data from the second external device based on the address from the destination address generator. A direct memory access device that writes data to an external device analyzes the contents of the data register, generates a status according to the analysis content, and generates a status to notify the first and second external devices. A direct memory access device characterized by being provided with a device.