JPH02217943A - Rapid cache memory - Google Patents

Abstract

PURPOSE:To reduce write-back operation time by scanning only an area written from a CPU to a cache memory at the time of write-back operation. CONSTITUTION:A first in first out(FIFO) memory 3 is used as a write address storing memory for storing an address at the time of write access of the CPU. A lower address written form the CPU is stored in the FIFO memory 3 and an address array 4 and a data array 5 corresponding only to the address stored in the FIFO memory 3 are scanned. Consequently, the write back operation time can be reduced and the operation speed of the cache memory can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention particularly relates to a cache memory that shortens the time between 9183728.17.

(Prior Art) Generally, a cache memory is provided between a CPU and a low-speed main memory and functions as a high-speed buffer memory. C
When the PU reads the main memory, the address and read data are stored in the cache memory, and then the PU reads the main memory.
When U reads the same address, it compares it with the address stored in the cache memory, and if they match, the CPU speeds up the processing by reading the data from the cache instead of from the main memory.

Writeback is when the CPU writes to main memory.
In reality, the address and data are stored only in the cache memory, and the contents are later transferred from the cache memory to the main memory.Next, an example of a conventional cache memory is shown in block diagrams in Figures 2 and 3. To explain, 10 is the lower order of the address bus and counter 3, which will be described later.
This is a multiplexer that switches the count output of 0.

Reference numeral 20 denotes a multiplexer that switches between the upper address bus and the address tag output of the address array 40, and the counter 30 scans the address array 40 and data array 50, which will be described later, during a write-back operation.

The address array 40 stores addresses held in the cache memory and their statuses, and is composed of a RAM.

The data array 50 stores data held in the cache memory and is composed of a RAM, and 60 is a comparator that compares the address stored in the address array 40 with the upper address of the address bus. 70 is a controller that controls switching of multiplexers 10 and 20, operation of counter 30, read/write of address array 40 and data array 50, main memory access, and CPU
control response behavior.

The fact that data at a certain address is in the cache memory means that the upper part of that address is stored in the address tag part of the address array 40 corresponding to the lower part of that address, and when this address is accessed by the CPU, the data of the comparator 60 is stored. The comparison result is a match. Further, the data at this time is stored in the data array 50 corresponding to the lower order of the address at this time, and furthermore, the fact that the address tag is valid is stored in the corresponding status section of the address array 40.

If there is a write from CP or U to that address, the corresponding status field also stores that there was a write (see FIG. 3).

Next, the access operation of the CPU will be explained. First, the address array 40 is in a read operation, and the CPU
When U starts accessing, the contents of the address array corresponding to the lower address from the CPU are read, and the address tag part is compared with the upper address from the CPU by the comparator 60. This comparison result and the state of the status section of the read address array 40, that is, CP
C depends on whether there is data at the address accessed by U, whether there is a write from the CPU, and whether the CPU access is read or write.
Various operations of the PU are performed.

Next, the write-back operation of the cache memory will be explained.

The contents of the address array 40 and data array 50 are scanned, and if the cache memory has been written by the CPU, the contents of the address tag are used as the upper address on the main memory side, and the count output of the counter 30 is used as the upper address on the main memory side. The contents of the data array 50 corresponding to the lower address are transferred to the main memory, and the status section is written to the state in which the cache memory was not written by the CPU.

(Problem to be Solved by the Invention) As described above, in the conventional cache memory, when writing back from the cache memory to the main memory, all areas that do not need to be written back must be scanned. Back operation time becomes longer and CP
The processing speed of U has decreased.

The present invention was invented under these circumstances, and the purpose of the write-back operation is to reduce the operation time during write-back by scanning only the area where the write to the cache memory has been performed from the CPU.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a write address storage memory that stores an address at the time of write access by a CPU, and provides information about the addresses stored in the write address storage memory. The feature is that only the address array is scanned.

(Function) During write-back, the address array and data array can be scanned using only write access addresses of the CPU.

(Example) Next, an embodiment of the present invention shown in FIG. 1 will be described.

Reference numeral 1 designates a first multiplexer for switching between the lower order of the address bus and the output of a FIFO memory 3, which will be described later. Reference numeral 2 designates a second multiplexer that switches between the upper order of the address bus and the address tag output of an address array 4, which will be described later.

The human output of the data in FIFO memory 3 is the so-called tir
It uses the st tn first out method, and stores the address to which the CPU has written, for example, the lower address. That is, a FIFO memory is used as a write address storage memory that stores addresses for write access by the CPU. The address array 4 is composed of a RAM, and stores the address held in the cache memory in the address tag part, whether the address tag part is valid, whether there is a write from the CPU, and the FIFO memory 31 address. 1ata is sent to the status section to indicate whether the

Reference numeral 5 denotes a data array for storing data held by the cache memory, and is composed of a RAM. A comparator 6 compares the address tag output of the address array 4 with the upper address of the address bus.

7 is a controller, and the first multiplexer 11
Switching of the second multiplexer 2 and FIFO memory 3
, read and write of address array 4 and data array 5, access to main memory, response operation to CPU, etc.

Next, the present invention will be explained in detail.

First, the access operation of the CPU will be explained.

Usually, the first multiplexer 1 and the second multiplexer 2 are connected on the address bus side.

The first operation is a read operation for the address array 4, and the following 58 types of operations are performed depending on the comparison value of the comparator 6, the state of the status section of the address array 4, and whether the CPU access is a read or write.

If the CPU access is a read and the data at the address accessed by the CPU is in the cache memory, the controller 7 reads that data from the data array 5,
Transmit the read data to the CPU. At this time, address array 4 and data array 5 are not updated.

If the CPU access is a read, and the data at the address accessed by the CPU is not in the cache, and the CPU has never written to the cache memory area accessed by the CPU, the controller 7 uses the address from the CPU to read the main memory. Read the read data to C
At the same time as transmitting the data to the PU, the data is written to the data array 5 corresponding to the address, and the upper address at that time is written in the address tag section of the corresponding address array 4.
Three messages are written in the status section to indicate that the address tag is valid and that the CPU has not written to that address. Whether or not the address is stored in the FIFO memory 3 remains unchanged.

If the access by the CPU is a read, and the data at the address accessed by the CPU is not in the cache memory, and the CPU has written an address in the cache memory corresponding to the accessed address, the controller 7 sends the data to the second multiplexer 2. is switched from the address bus to the input of the address array 4, the data array 5 is read, and the data previously written by the CPU is written to the main memory.

Next, the controller 7 switches the second multiplexer 2 to the upper address bus, and from this point on, when the CPU accesses are read, the data at the address accessed by the CPU is not in the cache memory, and the CPU has never written to that area. Perform the same action.

If the CPU access is a write and the data at the address accessed by the CPU is in the cache memory or the CPU has never written to that address, the controller 7 writes the write data to the data array 5, and The address is written to the address tag part of the address array 4, and the status part of the address array 4 is written to indicate that the address tag is white and that there has been a write from the CPU.

If the upper address of the lower address bus at that time is not stored in the FIFO memory 3, the address is written in the FIFO memory 3, and the fact that the address is stored in the FIFO memory 3 is written in the address array 4, respectively. If the lower address at that time is stored in the FIFO memory 3, it is not changed.

If the CPU access is a write and the data at the address accessed by the CP Ll is not in the cache memory, and the CPU has written to that address before, the controller 7 switches the second multiplexer 2 to the address array 4 side. , leading data array 5 and past C
Writes data written from PU to main memory.

Next, return the second multiplexer 2 to the upper address bus,
Write the CPU write data to data array 4, and
The upper address from the PU is sent to the address tag part of address array 4, and the address tag is valid in the status part.
Writes that there was a light from U.

Note that the contents of the FIFO memory 3 are not changed at this time.

Next, the write-back operation of the cache memory will be explained.

During write-back operation, the first multiplexer 1
, the second multiplexer 2 is switched and connected to the FIFO memory 3 and address array 4 side.

Under the control of the controller 7, the address array 4 and data array 5 are scanned based on the output of the FIFO memory 3, and if the cache memory has been written by the CPU, the data in the corresponding data array 5 is scanned from the address array. Write to the main memory using address tag section 4. This scanning is performed until the FIFO memory 3 becomes empty. Also, when writing to main memory ends,
A message indicating that no address is stored in the FIFO memory 3 is written in the status section of the address array 4.

In this way, the present invention stores the lower address to which the CPU has written in the FIFO memory 3, and
The address array 4 and data array 5 corresponding to only the addresses stored in the memory 3 are scanned.

[Effects of the Invention] According to the present invention, cache memory write-back is performed using an address array for only addresses from a memory that stores addresses written by a CPU or the like.
Since it is sufficient to scan the data array, the write hack operation time can be significantly reduced and the speed of the cache memory can be increased.

[Brief explanation of the drawing]

FIG. 1 shows one embodiment of the present invention, and is a block diagram showing the configuration. The third factor in FIG. 2 is a block diagram showing a conventional example. Data array, 6... Comparator, 7... Control O

Claims (1)

[Claims] A data array that stores data, an address array that stores addresses of data stored in the data array, and a comparator that compares the address from the address array with the address from the address bus,
When the address from the address array and the address from the address bus match as a result of the comparison by the comparator, the cache memory outputs the data of the data array corresponding to the matched address, and the write memory stores the address at the time of write access. The present invention is characterized by comprising an address storage memory and a controller that scans the address array and data array only for addresses stored in the write address storage memory during a write-back operation of the cache memory. Fast cache memory.