JPH10320274A - Cache flashing device, computer system provided with the device and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache flashing device capable of improving the performance of a system by shortening time required for cache flashing operation. SOLUTION: The addresses of all data blocks in a cache memory 20 are stored in any of plural areas A0 to An-1 included in an updating address storing part 32. When a certain cache block is turned to a dirty state after being temporarily turned to the dirty state, an updating address deleting part 34 deletes the address from its area. At the time of executing cache flashing, a full flash execution part successively extracts the addresses of dirty blocks from respective areas and issues a command for requesting the rewriting of data indicated by the addresses to a main memory 51 to a system bus 40, so that the contents of all dirty blocks are rewritten in the main memory 51.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache flush device for a cache memory having a snoop mechanism for ensuring data consistency, a fault-tolerant computer system and a recording medium provided with the device.

[0002]

2. Description of the Related Art Generally, a computer uses a cache memory for temporarily storing data required by a processor in order to speed up access to a main memory by the processor.

Normally, a cache memory holds data in data units of a predetermined size called cache blocks. In this case, management information called a cache tag is held, and the data of the cache block stored in the cache memory is changed by the processor, for example, which data in the wave main memory is different from the content of the main memory. Is managed (dirty state).

On the other hand, a computer provided with a plurality of processors (a so-called multiprocessor computer) also has a plurality of cache memories. In order to guarantee data consistency among these cache memories, a snoop mechanism is provided in each cache memory. Is provided.

[0005] The snoop mechanism checks whether a bus command issued to the bus does not affect data stored in its own cache memory, and whether it must return data stored in its own cache memory as a response. It monitors whether or not, and if necessary, invalidates the corresponding data.

[0006] By the way, there are copy-back type and write-through type cache memories. However, the data update by the processor is not immediately reflected in the main memory, but is kept inside for a certain period of time. In this case, data that is changed on the cache memory by the processor and is different from the content of the main memory is actively written back to the main memory (write
back) operation.

For example, when data stored in a cache memory is transferred to an input / output device having no snoop mechanism, write-back is required. The operation of writing back changed data from the data stored in the cache memory to the main memory is called a cache flush operation. A state in which data in the cache memory is changed is called a dirty state. The cache block in the dirty state is called a dirty block.

[0008] Such a cache flush operation includes:
This is useful for a checkpoint computer other than when transferring data to an input / output device that does not have a snoop mechanism. That is, in the case of a checkpoint-type computer that resumes processing from a previously acquired checkpoint when any failure occurs in the computer, a change that exists only in the cache memory at the time of the checkpoint is performed. It is necessary to write the data back to the main memory.

[0009] A cache flush operation is typically performed based on software containing cache flush instructions. By executing the software, the processor refers to the contents of the cache tag to determine whether or not each cache block is a dirty block. As a result, if the block is a dirty block, a cache flush operation for writing back the data of the corresponding cache block to the main memory is performed.

As described above, the processor determines the state of each of the cache blocks one by one according to a given program, and if the cache block is in a dirty state, writes it back to the main memory (cache flush). Operation) must be performed. It takes a very long time to process all the cache blocks.

This situation will be specifically described with reference to the following program example.

FIG. 32 shows an example of a program for performing a cache flush operation in the US SGI R4000 processor. In this program, "cac
He0x17,0 ($ 4) "
The cache block of the second cache corresponding to the address held in the fourth register (# 4) is selected. If the state of the cache block is dirty, its contents are written back to main memory,
The state becomes invalid. On the other hand, if it is not a dirty state, it will simply be an invalid state. This loop (loop
p) needs to be executed by the number of cache blocks of the secondary cache.

When the time required to process this loop is counted, the number of instructions is four, so four processor cycles are required, which is converted into two bus cycles (one bus clock). Execute two instructions). Therefore, the time for flushing all cache blocks does not include the time for writing data back to the main memory, and the cache flush time = the number of cache blocks × 2 bus cycles, which is a very time-consuming process.

On the other hand, in order to speed up the cache flush operation, the cache memory itself is modified. However, this method cannot increase the speed of an existing cache memory.

[0015]

As described above, in the conventional computer, the flush operation of the entire cache memory (writing back the contents of all dirty blocks to the main memory) is performed by software for all cache blocks. , A lot of processing time was spent.

Also, while the flash operation is being performed on the entire cache memory, the processor cannot execute other programs, so that the original data processing is stopped and the performance of the entire system is reduced. There was a problem that would be.

Particularly, in a computer adopting a method in which a cache flush operation must be performed at a checkpoint, an increase in the checkpoint processing time has been a serious problem.

The present invention has been made in view of the above points, and provides a cache flush apparatus which shortens the time required for a cache flush operation to improve system performance, a computer system including the same, and a recording medium. The purpose is to:

[0019]

[Means for Solving the Problems]

(1) According to a first aspect of the present invention, a cache flush device includes at least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, the processor, and the main processor. A cache flash device used in a computer comprising a system bus for connecting to a memory,
An update including a plurality of areas for storing addresses of data held by a dirty block which is a cache block holding data to be written back to the main memory among cache blocks secured in the cache memory. An address storage unit and a data update in the cache memory are detected by monitoring the system bus, and an update address and an identification number of the processor that has performed the data update are used in each area of the update address storage unit. An update address registering means for selecting any one of the areas and storing the update address in the selected area; and detecting the writing back of the data held by the dirty block to the main memory by monitoring the system bus, The write-back address and the above-mentioned professional who performed the write-back And a Tsu service identification number to select one of the regions in each region of the update address storage means,
Update address deletion means for deleting an update address that matches the write-back address stored in the selected area; and sequentially instructing all update addresses stored in the update address storage means when instructed by the processor. A flash execution means for issuing to the system bus a command for reading and writing back the data held by the dirty block indicated by the read update address to the main memory. .

In the first aspect, the addresses of all the dirty blocks in the cache memory are stored in one of a plurality of areas provided in the update address storage means by the update address registration means. Also, when a cache block once becomes dirty and then no longer dirty, the address is deleted from the area by the update address deletion means.

When performing a cache flush, the flush execution means sequentially takes out the address of the dirty block from each area and issues a command to the system bus to request the data indicated by the address to be written back to the main memory. As a result, the contents of all dirty blocks are written back to the main memory.

This eliminates the necessity of performing a process of sequentially determining whether or not all cache blocks are dirty blocks as in a conventional cache flush by software, so that a quick and efficient cache flush operation is performed. It becomes possible.

(2) According to a second aspect of the present invention, a cache flush device is a copy-back type having a bus snoop mechanism and at least one processor having a direct-mapped cache memory;
A cache flash device for use in a computer comprising a main memory and a system bus connecting the processor and the main memory, the cache flash device being provided corresponding to each cache block secured in the cache memory. A plurality of areas each for storing an address of data held by a dirty block which is a cache block in a state where data to be written back to the main memory is held, each area having one entry; Update address storage means, and data update in the cache memory are detected by monitoring the system bus, and each area of the update address storage means is determined based on the update address and the identification number of the processor which has performed the data update. Select one of the areas in the Update address registering means for registering the update address in the area, and writing back of the data held by the dirty block to the main memory is detected by monitoring the system bus, and the write back address and the write back are detected. Any one of the areas in the update address storage means is selected from the identification number of the processor, and when the update address registered in the selected area matches the write-back address, the area Update address deletion means for deleting the registered update address; and when instructed by the processor, sequentially read out all update addresses stored in the update address storage means, and read the dirty address indicated by the read update address. A command requesting that the data held by the block be written back to the main memory. The de characterized by comprising comprises a flash execution means for issuing to said system bus.

In the second aspect, for example, when the processor has a write buffer for temporarily storing a write request to the main memory, one cache block is viewed from the aforementioned cache flash device connected to the system bus. However, a situation occurs in which it looks as if a plurality of dirty blocks are stored at one time. The cache flush device of the present invention is designed to cope with such a situation. Each of the areas has only one entry, and this entry stores not the write buffer but the data stored in the cache block. Only the address (latest update address) is stored, and the update address deletion means is used when the latest update address stored by the update address registration means matches the write-back address issued to the system bus. Only the update address is deleted. In this manner, by configuring each area to have only one entry and ignoring a write-back request of an update address earlier than the latest issued from the write buffer to the system bus, an appropriate cache flush operation is ensured. Will be.

(3) According to a third aspect of the present invention, a cache flush device is a copy-back type having a bus snoop mechanism and at least one processor provided with a direct-mapped cache memory;
A cache flash device used for a computer comprising a main memory and a system bus connecting the processor and the main memory, provided for each cache block secured in the cache memory. An area for storing an address of data held by a dirty block which is a cache block in a state holding data to be written back to the main memory, each area having one entry; Update address storage means provided with a plurality of sets of counters provided corresponding to the areas; data update in the cache memory detected by monitoring the system bus; the update address and the identification of the processor which has performed the data update; Number of each of the above update address storage means And an update address registering means for storing the update address and incrementing the counter corresponding to the selected area, and writing back the data held by the dirty block to the main memory. Is detected by monitoring the system bus, and any one of the areas of the update address storage means is selected from the write-back address and the identification number of the processor that performed the write-back. The update address deletion means for decrementing the counter, and when instructed by the processor, the value of the counter corresponding to that area is stored in an area other than the initial value among the areas provided in the update address storage means. The update address is sequentially read, and the above-mentioned dirty data indicated by the read update address is read. A command requesting a write back to said main memory data block holds characterized by comprising comprises a flash execution means for issuing to said system bus.

The third aspect also considers the case where the processor has a write buffer. Each area has only one entry, and a counter is provided for each of these areas. Then, when storing the update address in a certain area, the update address registration means increments a counter corresponding to the area. On the other hand, the update address deletion means, when detecting the write-back, decrements the counter corresponding to the area. Then, the flash execution unit requests a write-back only for the update address registered in the area where the counter is not the initial value. That is, by managing the difference between the number of update blocks and the number of write-back blocks for each cache block, an appropriate cache flush operation is ensured even when a write buffer is applied.

In some systems, the contents of the dirty block cannot be written back to the main memory by issuing a command to the system bus. In this case, it is preferable to provide an update address reading means for sequentially reading all update addresses stored in the update address storage means and notifying the processor of the read update addresses, instead of the above-mentioned flash execution means. Even in this case, the provision of the means for notifying the processor of only the address of the dirty block in this way makes it possible to compare the cache block with a process of sequentially determining whether or not the cache block is a dirty block, as compared with the related art. A quick and efficient cache flush operation can be performed.

(4) According to a fourth aspect of the present invention, a cache flush device includes at least one copy-back type cache memory having a bus snoop mechanism.
A cache flash device for use in a computer comprising at least one processor, a main memory, and a system bus connecting the processor and the main memory, the cache flash device being a cache flash device secured in the cache memory. Update address storage means including a plurality of areas for storing addresses of data held by dirty blocks which are cache blocks in a state of holding data to be written back to the main memory;
The data update on the cache memory is detected by monitoring the system bus, and any one of the areas of the update address storage means is determined from the update address and the identification number of the processor that has performed the data update. Update address registration means for selecting and storing the update address in the selected area; and when the number of empty entries in the area selected by the update address registration means is less than a preset value, the update address is already stored in the area. Select one of the update addresses in the system bus, and issue a command to the system bus to request the data held by the dirty block indicated by the selected update address to be written back to the main memory. The entry release means (entry which makes the entry storing the update address a free entry. reclaim), and when instructed by the processor, sequentially reads all update addresses stored in the update address storage means, and transfers the data held by the dirty block indicated by the read update address to the main memory. Flash execution means for issuing a command requesting writing back to the system bus.

In the cache flush apparatus according to the fourth aspect of the present invention, a predetermined number (the number of entries in the area may be equal to the number of entries in the area, (The number may be any number within the range.)

That is, when a new update address is to be stored and the number of empty entries in the area falls below a preset number, the entry release means sets the update address of the already stored update address. Any one of them is selected, a write-back request for the selected update address is issued, and this entry is made empty. As described above, if a mechanism for issuing a write-back request for an update address in accordance with the use status of each area is provided, application to a cache memory that is not of the direct map type becomes easy, and the area provided by the update address storage means , The degree of freedom such as setting the number of entries and associating areas with addresses can be greatly expanded.

When the cache memory is constituted by an n-way set associative, a plurality of areas provided in the update address storage means may be provided as a pair in a group formed by n cache blocks. preferable. This is to realize simplification of hardware and high-speed processing.

(5) According to a fifth aspect of the present invention, a cache flush device comprises at least one copy-back type cache memory having a bus snoop mechanism.
A cache flash device for use in a computer comprising at least one processor, a main memory, and a system bus connecting the processor and the main memory, the cache flash device being a cache flash device secured in the cache memory. Update address storage means including a plurality of areas for storing addresses of data held by dirty blocks which are cache blocks in a state of holding data to be written back to the main memory;
The data update on the cache memory is detected by monitoring the system bus, and any one of the areas of the update address storage means is determined from the update address and the identification number of the processor that has performed the data update. Update address registering means for selecting and registering an update address in the selected area; and rewriting of the data held by the dirty block to the main memory is detected by monitoring of the system bus. Any one of the areas of the update address storage means is selected from the identification number of the returned processor and the write-back address is searched by searching the selected area within a predetermined period. Update address deletion means for deleting an update address when an update address matching the update address is detected When the number of vacant entries in the area selected by the update address registering means is smaller than a preset value, one of the already registered update addresses is selected, and the selected update address is used. An entry release means for issuing to the system bus a command requesting a write-back of the data held by the indicated dirty block to the main memory, and setting the entry storing the updated address to a free entry; When instructed by the processor, sequentially read all update addresses stored in the update address storage means, and request to write back the data held by the dirty blocks indicated by the read update addresses to the main memory. Executing means for issuing a command to be executed to the system bus. Characterized by comprising comprises a.

In the fifth aspect, when the update address deletion means detects a command requesting write-back, the update address deletion means searches an area corresponding to the write-back address within a predetermined period, and executes the write-back. When an update address that matches the address is detected, the update address is removed (nothing is performed when the update address is not detected). In this case, there is a possibility that update addresses that are no longer dirty blocks will continue to be stored in the area, but the entry release means will manage the number of empty entries and actively secure empty entries. Even if the flash execution means issues a command to write back the address that is no longer a dirty block, there is no problem since none of the cache memories responds to this command. . On the other hand, since the time spent by the update address deletion means for the deletion processing is kept within a predetermined range, other processing is not adversely affected even when the frequency of access to the main memory is extremely high.

Note that this update address deletion means does not execute deletion processing within a predetermined period,
It is also effective to continue executing the cache memory device until it detects a command to be processed next. According to this, it is possible to prevent other processes from being adversely affected, and to continue / interrupt the process of deleting the update address stored unnecessarily more appropriately.

In addition to the above-described detection of a command requesting a write-back, the update address deletion unit detects a read command issued when a cache miss occurs, for example, and determines the target of the command. It is preferable to search for an address that is not registered as an update address in the area and delete it when detected. Since the data indicated by the target address of the read command issued when the cache miss occurs can be determined to be in a clean state, if such a command is used as a trigger, unnecessary update addresses are deleted. The frequency of executing the process can be increased, and the process of releasing the entry and the flushing operation of the cache can be reduced.

Also, for example, depending on the expected dirty rate of the cache memory, even if the number of entries in each area is smaller than the corresponding number of cache blocks, there is no problem in performance. If the number of entries in the area is made smaller than the number of corresponding cache blocks, the amount of hardware to be provided can be reduced.

In some cases, it is effective to configure a plurality of areas included in the update address storage means so that they can be selected only by the update address. For example, depending on the specifications of the system bus, the identification number of the processor may not be obtained only by monitoring the system bus.
That is, even in such a case, the cache flash device can be applied.

(6) According to a sixth aspect of the present invention, in the cache flash device, the update address storage means may store the dirty block corresponding to each area for storing an address of data held by the dirty block. A dirty block counter for holding the number of blocks; the update address registering means having an incrementing means for incrementing the dirty block counter corresponding to the selected area; and The write-back to the main memory is detected by monitoring the system bus, and one of the areas of the update address storage means is determined from the write-back address and the identification number of the processor that has performed the write-back. Select the dirty row corresponding to the selected area. Decrement means for decrementing the dirty counter, and when the dirty block counter becomes an initial value by the decrement of the decrement means, all the entries storing the update address in the area corresponding to the dirty block counter are vacant entries. Characterized by further comprising entry batch release means.

In the sixth aspect, by managing the dirty block counter, it can be detected that all the update addresses registered in a certain area do not need to be written back to the main memory. If the entry batch release unit leaves all entries empty and reduces the operation opportunity of the entry release unit, it is possible to improve the performance of the entire computer.

(7) According to the seventh aspect of the present invention, in the cache flash device, the update address storage means may store the dirty block corresponding to each area for storing an address of data held by the dirty block. A dirty block counter for holding the number of blocks, the update address registering means has increment means for incrementing the dirty block counter corresponding to the selected area, and the update address deleting means has And a decrement means for decrementing the dirty block counter corresponding to the selected area. When the dirty block counter becomes an initial value by the decrement of the decrement means, the dirty block counter is stored in an area corresponding to the dirty block counter. Update ad Characterized by further comprising comprises a bulk delete means for deleting all of the scan.

In the seventh aspect, by managing the dirty block counter, it is possible to detect that all the update addresses registered in a certain area do not need to be written back to the main memory. If the entry batch release unit leaves all entries empty and reduces the operation opportunity of the entry release unit, it is possible to improve the performance of the entire computer.

Also, instead of when all the update addresses stored in a certain area do not need to be rewritten, the number of stored update addresses increases beyond the value of the dirty block counter beyond a predetermined value. It is also effective to have the entry release means release a certain number of update addresses when this occurs. In this case, it is possible to avoid storing an update address that does not need to be rewritten beyond a predetermined amount and to reduce the number of commands issued unnecessarily during a cache flush operation.

(8) According to an eighth aspect of the present invention, a computer system includes at least one or more processors having a copy-back type cache memory having a bus snoop mechanism, a main memory, and the processor. 14. A computer system comprising a system bus for connecting to the main memory and periodically collecting checkpoints for restarting interrupted processing, wherein the computer bus comprises: Any one of the cache flush devices described above, data processing means for executing normal data processing while causing the cache flush device to capture an update address, and a main of a context during data processing executed by all of the processors in synchronization. Storing in a memory and executing the flush execution means of the cache flush device Checkpoint creation means including writing back the data held by all the dirty blocks to the main memory; and, when a failure occurs, restoring the main memory at the time of the checkpoint collected immediately before. And rollback recovery means for resuming data processing using the information held in the main memory.

In the eighth aspect, in a computer system that periodically collects checkpoints for restarting interrupted processing, it is important how to reduce the time spent for collecting checkpoints. And
Most of this checkpoint collection processing is occupied by cache flush operations. That is, if the above-described cache flush device is applied to such a computer system, the performance of the entire system can be improved.

It is preferable to apply the above-described cache flush device to a computer system having a plurality of computers such as a master system and a slave system in addition to periodically collecting check points. This is because the time required for checkpoint collection can be shortened, so that the performance of the entire system can be improved. Furthermore, if the computer executes the flush execution means of the cache flush device in the data processing normally executed, the time required for checkpoint collection can be further reduced.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment.

A plurality (here, 3) having a copy-back type cache memory 20 with cache coherency
Processor 10 is connected to system bus 40. Here, in the case where the cache memory is configured by two or more hierarchies of a primary and a secondary, the cache memory according to the present embodiment refers to the cache memory closest to the system bus 40. Also,
Some cache memories are divided into a cache memory for storing instructions and a cache memory for storing data. In this case, the cache memory according to the present embodiment is a cache for storing data. Refers to memory. Also, the address on the system bus 40 in the present system will be described as 32 bits.

The cache bus device 30 and a memory controller 50 connected to the main memory 51 are also connected to the system bus 40. The cache flash device 30 includes a bus interface 31, an update address storage unit 32 (composed of areas A0 to An-1), an update address registration unit 33, an update address deletion unit 34, and a flash execution unit 35.

The update address registration section 33 and the update address deletion section 34 are implemented as one type of hardware module with the above-described functions.

The bus interface 31 controls an interface with the system bus 40.

The update address storage unit 32 has n areas A for holding the addresses of all dirty blocks.
0 to An-1. In this example, the addresses of all dirty blocks are stored in the update address storage unit 32, and addresses that are not dirty are not stored in the update address storage unit 32.

Here, the structure of the region will be described. As shown in FIGS. 2A and 2B, the area Ai has one or more entries for storing an update address. Although it is necessary to indicate whether the value stored in each entry is valid or not, this method is suitably based on one of the following two methods.

(1) An entry in which an update address is not stored usually has a value that can never be taken (for example, 0x
FFFFFFFF) is stored (FIG. 2A).

(2) A flag indicating whether the contents of the entry is valid (valid or invalid) is attached to each entry separately from the entry for storing the address (FIG. 2B).

It should be noted that a detailed description will be given later of how to provide the area constituting the update address storage unit 32 and the correspondence between the address and the area.

FIG. 3 shows an operation procedure of the update address registration unit 33. When the processor 10 detects a command indicating that data has been updated in the cache memory 20 by writing data (step A1), the processor 10 writes the command based on the updated address (update address) and the identification number of the updated processor. Then, one of the n areas (A0 to An-1) constituting the update address storage unit 32 is selected (step A2), and the identification number of the processor 10 that has performed the update belonging to the selected area is obtained. There are the following two cases depending on the specifications of the system bus.

(1) In the case of being included in the above command (2) In the case of being obtained by monitoring the signal of bus arbitration FIG. When a command for writing back the contents of the dirty block to the main memory is detected (step B1), the update address is stored based on the address at which the write-back occurred (the write-back address) and the identification number of the processor that performed the write-back. N regions (A0 to An-1) configuring the unit 32
Is selected (step B2), an entry including the address is searched for among the entries included in the area, and the updated address is deleted (step B3).

The update address registration unit 33 and the update address deletion unit 34 store any one of n areas (A0 to An-1) constituting the update address storage unit 32 from the processor identification number and the address. In selecting the method, the same method must be used. The reason why the update address storage unit 32 is configured with n areas is as follows.
This is because the operation of the update address deletion unit 34 searching for an entry including the write-back address and deleting the entry is as fast as the cache memory.

FIG. 5 shows the operation procedure of the flash execution unit 35.

The flash execution unit 35 requests to sequentially fetch all addresses stored in the update address storage unit 32 based on an instruction from the processor and write back the contents of the dirty block having the addresses to the main memory. Command to issue to the system bus. Therefore, the variable i indicating the area is set to 0 in step C1, and it is determined whether or not the area Ai has an update address in step C2. If yes, the update address included in the area Ai is taken out in step C3, a command is issued to request the contents of the dirty block at that address to be written back to the main memory, and the process returns to step C2. If the answer is no in step C2, the variable i is incremented in step C4, and in step C5, it is determined whether or not i = n in order to determine whether or not the processing of all the areas has been completed. If no,
Returning to step C2, if yes, end.

The process of deleting the fetched address from the update address storage unit 32 may be executed by the flash execution unit 35. However, the command issued by the flash execution unit 35 to request writing back to the main memory 51 may be executed. It is also possible that the update address deletion unit 34 detects this.

Next, the cache flush device 3 of this embodiment
The operation will be described based on the control method of “0”.

(Initialization) The processor 10 performs initialization so that the state of the cache memory 20 and the contents of the update address storage unit 32 of the cache flash device 30 match before operating the cache flash device 30. In the initialization, all cache blocks are invalidated. The areas A0 to An-1 are initialized so as not to include the update address.

(Normal Operation of Cache Flash Device 30) After the processor 10 performs initialization, the components constituting the cache flash device 30 perform predetermined operations, so that the update address storage unit 32 Of the dirty block is held. Conversely, a dirty block always exists for the update address stored in the update address storage unit 32. It will be described. Here, a case where a certain processor 10 updates data in the cache memory 20 is considered.

(1) If the cache memory 20 does not hold the data to be updated, the cache memory 20 requests the data at the address and also requests the other cache memories 20 to invalidate the data at the address. A command is issued to the system bus 40. When data is supplied to the cache memory 20, the cache block changes to a dirty state. The update address registration unit 33 captures the command via the bus interface 31, selects one of the areas A0 to An-1 based on the update address and the processor identification number, and stores the address in a free entry of the area. Write.

(2) If the cache memory 20 holds data to be updated in a shared state, a command requesting the other cache memories 20 to invalidate the data at the address is sent to the system bus 40. Issued to Then, when there is a response from another cache memory 20, the state of the cache block changes to dirty. The update address registration unit 33 captures the command via the bus interface, and based on the update address and the processor identification number, the areas A0 to A
n-1 is selected, and the above address is written in that area.

(3) If the cache memory 20 already holds data to be updated in a dirty state,
No command indicating data update is issued on the system bus 40, and therefore, the cache flush device 30 does not perform any operation. However, when the address of the cache block changes from a state other than the dirty state to the dirty state, the address is stored in any of the areas A0 to An-1, so that no problem occurs.

Depending on the cache memory, in addition to the above-mentioned states (1) to (3), Clean Exclu may be used.
There is one that can take a state called “sive”. Clean
The exclusive state indicates that the content of the cache memory is the same as that of the main memory, and that the cache memory holding the data at the address is only the cache memory. The reason why the cache block enters the Clean Exclusive state is that when a cache miss occurs when the processor attempts to read data and a command requesting the data is issued to the system bus, any of the cache memories is "held with the data". Is not returned.

When the cache block is Clean Exc
When data is written to the cache block in the active state, the cache bus corresponding to the address does not exist in the other cache memory, and therefore a command indicating data update is issued to the system bus. The cache block changes to a dirty state without being issued.

Therefore, in this example, Clean Ex
When using a cache memory that can take a positive state, the cache block must be a Clean Exc.
It is necessary not to be in a live state. It adds a function to the cache flash device 30 to return a response "having that data" to a command that requests a data from the system bus when a cache memory causes a cache miss by reading data from the processor. It can be realized by doing.

When the contents of a certain dirty block are written back to the main memory 51, the update address deletion unit 34 detects the command and the update address registration unit 33 detects the command based on the write back address and the processor identification number. The areas A0 to An-1 are selected in the same manner as the areas A0 to An-1 are selected.
An-1 is selected, and the same address contained therein is deleted.

(Cache Flush Operation by Cache Flush Device 30) When the processor 10 commands the cache flush device 30 to perform a cache flush, the flush execution unit 35 is stored in the update address storage unit 32 based on an instruction from the processor 10. A command is issued to the system bus 40 requesting that the addresses of the dirty blocks having the addresses are sequentially fetched and written back to the main memory 51.

As a result, there is no dirty block,
In addition, the process returns to the initial state in which the update address is not stored in the update address storage unit 32.

In this embodiment, the setting method of the areas A0 to An-1 constituting the update address storage unit 32 and the correspondence between the addresses and the areas are determined by the cache memory 2
It is desirable to match the configuration of 0. Next, it will be described.

(Area Design Method 1) First, the simplest case in which the cache memory 20 is a direct map system and the number of processors is 1 will be described. Now 1
It is assumed that the size of one cache block is B bytes and the number of cache blocks is M. In this case, in a normal cache memory, the data at address a is
It is stored in the (a / B mod M) th cache block.

In this case, the areas A0 to An-1 are provided in one-to-one correspondence with the cache blocks. That is,
When the number n of areas is equal to the number M of cache blocks,
The data at address a is stored in the (a / B mod M) -th area. Since the number of processors is 1, the update address registration unit 33 and the update address deletion unit 34 do not need to use the processor identification number.

Here, it is necessary to deal with a cache memory having a mechanism called a write buffer provided in a recent processor, which will be described.

The write buffer is a buffer for temporarily storing a data write request from the processor and the cache memory to the main memory. By providing a write buffer, if a write miss occurs when the processor attempts to update data at another address with respect to the dirty block, the data to be updated is first read from the main memory, and then the original dirty block is updated. Will be written back to the main memory.
In other words, from the viewpoint of the processor, the data to be newly updated becomes available immediately, and the performance is improved accordingly.

In a recent processor, two or more write buffers are provided. Therefore, when data is updated at various addresses corresponding to the same cache block one after another, data to be updated is read from the main memory one after another. Thereafter, the dirty block may be written back continuously.

Therefore, in the cache flash device 30 observing the system bus 40, the update address for one area is equal to the number of write buffers + 1.
Because it only temporarily appears to exist
Countermeasures are needed.

The simplest measure is to increase the number of entries in each area, but has the following problems.

(1) Since the number of entries is increased, the amount of hardware is increased.

(2) It is difficult to speed up finding an address that has been written back to the main memory from many entries.

If the cache memory is of the direct map type, the following two specific examples are effective for a cache memory having a write buffer mechanism.

(Specific Example 1) Here, it is assumed that the number of entries in each area is one. FIG. 6 shows an operation procedure of the cache flash device 30 when the update address registration unit 33 detects a command indicating data update, and the update address deletion unit 34.
The operation procedure will be described with reference to FIG. 7 showing the operation procedure of the cache flash device 30 when the command indicating that the dirty block is written back to the main memory 51 is detected.

(1) Upon detecting a command indicating data update, the update address registration unit 33 writes the update address in the entry of the corresponding area (FIG. 6).

(2) Upon detecting a command to write back the contents of the dirty block to the main memory 51, the update address deletion unit 34 compares the contents of the entry in the corresponding area with the write-back address. If they match, the content of the entry is changed to a state of an empty entry (FIG. 7).

(3) For each area, when the entry of the area is not an empty entry, the flash execution unit 35 sends to the system bus 40 a command requesting that the contents of the dirty block at that address be written back to the main memory 51. Issue.

Here, referring to FIG.
Will be described in the case where data D0, D1 and D2 are continuously written at address 0, address B × M, and address 2B × M, respectively. Where B is the size of the cache block, M
Is the number of cache blocks of the processor.

(1) The processor 10 attempts to write the data D0 at the address 0, but the data at the address 0 is not stored in the cache block 0.
At 0, the main memory 51 or the cache memory 20 of another processor 10 (in this case, the number of processors is 1, so it does not actually occur from another processor 10). And issues a command to the system bus 40 to notify the other processors 10 that the data is to be updated.

(2) As a result, cache block 0
The data from address 0 to address (B-1) is stored in a dirty state, and the data at address 0 is updated to D0. In the area A0, an updated address 0 is stored in correspondence with the update of the address 0.

(3) The processor 10 tries to write the data D1 at the address B × M, but the cache block 0
Since the data at address xM has not been stored, a write request to the main memory 51 for writing back the data at address 0, which is currently held in a dirty state, to the main memory 51 is stored in the write buffer. Also, in the system bus 40, in the main memory 51 or the cache memory 20 of another processor 10 (in this case, since the number of processors is 1, it does not actually occur from the other processor 10), the address B × M From (B × M + B−
1) Requests data at an address and issues a command to the system bus 40 to notify another processor 10 that data is to be updated.

(4) As a result, cache block 0
The data from the address B × M to the address (B × M + B−1) is stored in a dirty state, and the data at the address B × M is updated to D1. In the area A0, B ×
B × M is stored in correspondence with the update of the address M.

(5) The processor 10 attempts to write the data D2 at the address 2B × M,
Since the data at the address B × M was not stored, a write access request to the main memory 51 for writing back the data at the address B × M currently held in the dirty state to the main memory 51 is sent to the write buffer. Is stored.
As a result, two commands for writing back to the main memory 51 are stored in the write buffer. In addition, the main memory 51 or the cache memory 20 of another processor 10 is connected to the system bus 40 (in this case,
Since the number of processors is 1, it does not actually occur from another processor 10). From address 2B × M (2
A request for the data at the address of (B × M + B-1) is issued, and a command to update the data to another processor 10 is issued to the system bus 40. (6) As a result, data from address 2B × M to address (2B × M + B−1) is stored in the cache block 0 in a dirty state, and the data at address 2B × M is updated to D2. In the area A0, 2B × M is stored in correspondence with the update of the address 2B × M.

(7) Stored in the write buffer,
A command to write back data from address 0 to address (B-1) to the main memory 51 is issued to the system bus 40. The update address deletion unit 34 does nothing because the content 2B × M of the area A0 does not match the write-back address 0.

(8) Stored in the write buffer,
A command for writing back data from the address B × M to the address (B × M + B−1) to the main memory 51 is issued to the system bus 40. The update address deletion unit 34 does nothing because the content 2B × M of the area A0 does not match the write-back address B × M.

[0098] The first embodiment has been described above.

(Specific Example 2) Here, the number of entries in each area is set to 1, and a counter indicating the number of update addresses corresponding to the area is provided. Entries and counters are used as follows.

(1) The counter 0 indicates that there is no update address included in the area.

(2) When detecting the data update, the update address registration unit 33 writes the update address in the entry of the corresponding area and increments the counter of that area by one. (3) When detecting that the contents of the dirty block are written back to the main memory 51, the update address deletion unit 34 decrements the counter of the corresponding area by one.

(4) For each area, when the counter of that area is not 0, the flash execution unit 35 issues a command to the system bus 40 requesting that the contents of the dirty block at that address be written back to the main memory 51. I do.

FIG. 9 shows the structure of the region Ai. A 4-bit counter is provided for a 32-bit entry.

FIG. 10 shows the operation procedure of the cache flash device 30 when the update address registration unit 33 detects a command indicating data update, and FIG.
4 shows an operation procedure of the cache flash device 30 when detecting a command indicating writing back of a dirty block to the main memory 51, and FIG. 12 shows an operation procedure of the flash execution unit 35, respectively.

Next, referring to FIG.
Will be described in the case where data D0, D1 and D2 are continuously written at address 0, address B × M, and address 2B × M, respectively. Where B is the size of the cache block, M
Is the number of cache blocks of the processor.

(1) The processor 10 attempts to write the data D0 at the address 0, but since the data at the address 0 is not stored in the cache block 0, the system bus 4
At 0, the main memory 51 or the cache memory 20 of another processor 10 (in this case, the number of processors is 1, so it does not actually occur from another processor 10). And issues a command to the system bus 40 to notify the other processors 10 that the data is to be updated.

(2) As a result, cache block 0
The data from address 0 to address (B-1) is stored in a dirty state, and the data at address 0 is updated to D0. In addition, 0 is stored in the area A0 in correspondence with the update of the address 0, and the value of the counter is incremented by 1 to become 1.

(3) The processor 10 tried to write the data D1 at the address B × M, but the cache block 0
Since the data at address xM has not been stored, a write access request to the main memory 51 for writing back the data at address 0, which is currently held in a dirty state, to the main memory 51 is stored in the write buffer. . Also,
In the system bus 40, the main memory 51 or the cache memory 20 of the other processor 10 (in this case, the number of processors is 1, so it does not actually occur from the other processor 10). B × M
+ B-1) Requests the data at the address, and issues a command to the other processor 10 to update the data to the system bus 40.

(4) As a result, cache block 0
The data from the address B × M to the address (B × M + B−1) is stored in a dirty state, and the data at the address B × M is updated to D1. In the area A0, B ×
B × M is stored in correspondence with the update of the address M. Further, the value of the counter is incremented by 1 to become 2.

(5) The processor 10 attempts to write the data D2 at the address 2B × M,
Since the data at the address B × M was not stored, a write access request to the main memory 51 for writing back the data at the address B × M currently held in the dirty state to the main memory 51 is sent to the write buffer. Is stored.
As a result, two commands for writing back to the main memory 51 are stored in the write buffer. Further, in the system bus 40, the main memory 51 or the cache memory 20 of another processor 10 (in this case, since the number of processors is 1, it does not actually occur from the other processor 10). (2
A request for the data at the address of (B × M + B-1) is issued, and a command to update the data to another processor 10 is issued to the system bus 40. (6) As a result, data from address 2B × M to address (2B × M + B−1) is stored in the cache block 0 in a dirty state, and the data at address 2B × M is updated to D2. In the area A0, 2B × M is stored in correspondence with the update of the address 2B × M. Further, the value of the counter is incremented by 1 to become 3.

(7) The data stored in the write buffer
A command to write back data from address 0 to address (B-1) to the main memory 51 is issued to the system bus 40. The value of the counter corresponding to the area A0 is decremented by one to two.

(8) The data stored in the write buffer
A command for writing back data from the address B × M to the address (B × M + B−1) to the main memory 51 is issued to the system bus 40. Further, the value of the counter corresponding to the area A0 is decremented by 1 to become 1.

In the above, the specific example 2 has been described.

(Area Design Method 2) Next, a case where the cache memory 20 is of the direct map system and the number of processors is P will be described. In this case, it is assumed that the size of one cache block is B bytes and the number of cache blocks is M.

In this case, there are two specific examples.

(Specific Example 3) The number n of regions is P × M,
Assume that the number of entries in each area is one. Then, the first M areas are stored in the cache memory 20 of the first processor 10.
Then, the next M areas are made to correspond to the cache memory 20 of the second processor 10, and so on.

The update address registration unit 33 and the update address deletion unit 34 may select an area based on the processor identification number and the address as described above. Each area is 1
Since it is associated with one cache block of one processor 10, in dealing with the write buffer of the processor 10, the specific examples 1 and 2 described above are used.
Is valid.

(Specific Example 4) The number n of areas is M, and the number of entries in each area is P. The area Ai corresponds to the i-th cache block of each processor 10.

By making such a correspondence,
Regardless of which processor 10 has generated the data update, the corresponding area is obtained from the updated address, so that unlike the first candidate, the processor identification number is not required. Therefore, the present invention is also effective in a case where the identification number of the processor that has updated the data cannot be obtained due to the specifications of the system bus.

However, in dealing with the write buffer of the processor, the specific examples 1 and 2 described above are used.
There is a problem that is not applicable. Therefore, it is preferable that the processor having the write buffer be based on the specific example 3 or the second to fourth embodiments described later.

(Area Design Method 3) Next, a case where the cache memory is N-way set associative, the number of cache blocks is M, and the number of processors is 1 will be described. The size of one cache block is B
Assume it is a byte. In this case, the N cache blocks form a group, and the data at address a is:
((A / B) mod (M / N))-th group of cache blocks.

(Specific Example 5) In this case, the number n of areas is M
/ N, and the number of entries in each area is N. The data at the address a is ((a / B) mod (M /
N)) is stored in the th area. The disadvantage of this method is that when the processor 10 has a write buffer, there is no improvement as in the case of the direct mapped cache memory 20. In order to solve this problem, it is desirable to use the method shown in the second to fourth embodiments described below.

(Specific Example 6) Even if the cache memory 20 is set associative, if the way in which the update address is stored can be determined by means of observing the control signal line of the system bus 40, the direct As in the case of the map, it is possible to set an area for each cache block. In that case, in dealing with the write buffer of the processor 10, the wand string example 1 and the specific example 2 described above are effective.

A comparison between the cache flush processing by the cache flush apparatus 30 of the present embodiment described above and the cache flush processing by the conventional software shows that the rate at which the cache blocks are dirty is very high, for example, exceeding 50%. Since there are many processes for writing back the contents of the dirty block to the main memory 51, there is no great difference in the required time.

On the other hand, if the rate at which a cache block is dirty is, for example, 10%, it takes 2 bus cycles × 10 = 20 cycles on average to find the next dirty block in cache flush by software. On the other hand, the flush execution unit 35 of the cache flush device 30 of the present embodiment
The speed of sequentially fetching the addresses stored in n-1 (tag search) can be increased by, for example, hardware for checking a plurality of areas in parallel, so that the cache flush processing time can be reduced.

The tag search time can be shortened by providing additional information other than the addresses in the areas A0 to An-1. This example will be described in a second embodiment.

Another advantage of the present cache flush device is that the processor can execute a normal process while causing the cache flush device to perform the cache flush process because the dedicated hardware is provided. This is particularly effective when the cache flush device of the present embodiment is applied to a fault-tolerant computer system employing a checkpoint method. This will be described in the fifth and sixth embodiments.

In the cache flush device 30 described above, the flush execution unit 35 sends a command to the dirty block to request that the data held therein be written back to the main memory 51. It is premised that the cache flush can be executed by issuing the cache flush to the cache.

In a normal system, a command such as Read-line that requests data reading while maintaining data consistency between caches corresponds to the command. There are two types of responses to the Read-line.

One is that the contents of the dirty block are issued to the system bus, and the main memory is updated at the same time.

The other is Retry (a little later, R
Executing "ad-Line") is issued to the system bus. Next, the cache memory to which the dirty block belongs voluntarily issues a Write-Line command to the system bus, and writes the contents of the dirty block back to the main memory. Then, the side receiving the Retry receives the R again.
When the head-line is issued to the system bus, the main memory responds with the latest data.

However, depending on the computer system, even if the Read-Line command is issued to the system bus, the contents of the dirty block may not be written back to the main memory and may be kept in the dirty block. Therefore, here, 2 of the cache flush device 30 applicable to such a computer system is described.
Two specific examples will be described.

(Specific Example 7) Cache Flash Device 3
0 performs a cache flush, first,
-A command to read the data of the dirty block called a Line-with-Invalidate command and issue a command to invalidate the contents of the dirty block, and then issue a Write-Line command, so that the previously read data is Memory 51
It is a method of writing back to. In this method, in order to maintain data consistency, the cache flush device 30 itself uses the cache memory 2 as if it had a dirty block.
It must behave like 0.

Read-Line-with-Invalidate to Write-Line In this method, the cache flush device needs to operate like a cache in order to maintain data consistency.

Read-Line to Write-Line (Write-Line unconditionally includes Invalidate) This method is designed with UltraSPARC version MBT. According to this method, an operation such as a cache is not required, and the hardware configuration is simple.

(Embodiment 8) In the second configuration method, first, the processor 10 is enabled to acquire all update addresses stored in the update address storage unit 32. For example, as shown in FIG. 14, the update address reading unit 37 having a function of sequentially reading all update addresses stored in the update address storage unit 32 is changed to the flash execution unit 3.
5 is provided in the cache flash device 30 instead of 5, so that the processor can read the update address stored in the update address reading unit 37. The update address reading unit 37 prepares a new update address every time the processor reads the update address. Furthermore, when the update address is read by the processor, it is possible to read a plurality of update addresses at a time to further increase the speed. Then, the processor 10 determines that the update address reading unit 3
7, the content of the dirty block is written back to the main memory.

At this time, the processor 10 causes the replacement of the cache block by using a cache operation instruction or by reading out the data of another address stored in the same cache block as the update address from the main memory. By repeating this until there is no more updated address, all dirty blocks can be written back to the main memory. The information that the update address has disappeared is read by the processor from the update address reading unit 37 in the same manner as the update address.

This method uses the cache flush device 3
0 has the advantage of simplifying the hardware since there is no need to manage data consistency. Further, compared with the conventional method in which the processor 10 executes all the processing by software, the dirty flash can be found more efficiently, so that the cache flush processing is faster.

FIG. 15 is a flowchart showing the operation of the embodiment 8.

Hereinafter, another embodiment of the present invention will be described.
In the following description, portions corresponding to those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

(Second Embodiment) Next, a second embodiment of the present invention will be described. FIG. 16 shows a system configuration of a computer system according to the second embodiment of this invention. The configuration of the computer to which the cache flush device 30 is applied is the same as that of the first embodiment.

The cache flash device 30 includes a bus interface 31 and an update address storage unit 32 (area A0).
To An-1), an update address registration unit 33, a flash execution unit 35, and an entry release unit 36.

The update address storage unit 32 is composed of n areas (areas A0 to An-1) for holding addresses of all dirty blocks. In the present embodiment, the addresses of all dirty blocks are stored in the update address storage unit 32. In addition, addresses that were once dirty blocks but are no longer valid are stored in the update address storage unit 32. May be stored. This is because this embodiment does not include the update address deletion unit 34 shown in the first embodiment, and this is a fundamental difference from the first embodiment.

Here, the structure of the region Ai will be described. In order to indicate whether the value stored in each entry of the area Ai is valid, the method described in the first embodiment can be employed, but it is more preferable to use the following method. .

That is, a plurality of entries constituting an area are used as a circular buffer. Read pointer (R
Pointer) and a write pointer (W pointer),
The updated address is stored from the entry pointed to by the R pointer to the entry immediately before the entry pointed to by the W pointer. However, when the W pointer and the R pointer match, it is not known whether this indicates a state where all entries are empty or all entries are not empty. A 1-bit flag is also provided. This method has an advantage that the operations of the update address registration unit 33 and the flash execution unit 35 are easily accelerated.

FIG. 17 is a conceptual diagram showing the structure of the area according to the present embodiment. The R pointer indicates the oldest registered update address among valid update addresses. The W pointer indicates a position where a new update address should be registered. When the W pointer and the R pointer match, the full flag indicates that all entries are empty (full flag = OFF) or that all entries are not empty (full flag = ON).

The update address registration section 33 is the same as in the first embodiment.

When the update address registering unit 33 attempts to write an update address in a certain area and detects that there is no free entry belonging to the area, the entry release unit 36 stores the update address stored in the area. And issues a command to the system bus 40 requesting that the contents of the dirty block having that address be written back to the main memory 51. At this time,
The entry holding the address is vacated. It is most efficient that the entry release unit 36 releases the entries at the above timing, but it is also possible to perform the release at an earlier timing such that a few empty entries still remain.

FIG. 18 shows a processing flow of the update address registration unit 33 and the entry release unit 36 when the update address registration unit 33 detects a command indicating that data update has occurred in the cache memory 20. When a command indicating data update is detected in step I1, a corresponding area Ai is obtained from the processor identification number and the update address in step I2. In step I3, it is determined whether or not the full flag of the area Ai is ON. If no, step I
If the answer is YES, in step I4, the entry release unit 36 issues a command requesting the dirty block to be written back to the main memory using the address in the entry indicated by the R pointer of the area Ai. In step I5, it is determined whether or not the R pointer points to the last entry. If no, the R pointer is incremented by 1 in step I6. If yes, step R8 is executed after the R pointer points to the first entry in step I7. In step I8, the update address is registered at the position indicated by the W pointer.

At step I9, it is determined whether or not the W pointer points to the last entry. If no, the W pointer is incremented by 1 in step I10, and if yes, step W11 is performed after the W pointer points to the first entry in step I11.
In step I12, it is determined whether or not the positions indicated by the W pointer and the R pointer are equal. If equal, step I
At 13, the full flag is turned on, and the processing ends. If they are not equal, the processing ends immediately.

The processing flow of the flash execution unit 35 is shown in FIG.
9 The flash execution unit 35 sequentially fetches all addresses stored in the update address storage unit 32 based on an instruction from the processor 10 (as a result,
The read address is erased from the update address storage unit 32 (steps J2 to J10), and a command is issued to the system bus 40 requesting that the contents of the dirty block at that address be written back to the main memory 51 (step J2). Step J5).

In this embodiment, for each area Ai,
Since the effective update address is stored only in the entry pointed to by the R pointer to the W pointer, the dirty block address can be efficiently extracted even when the percentage of dirty blocks existing is small, and the cache flush can be performed at high speed. Be transformed into

Next, the operation of the cache flash device 30 according to the present embodiment will be described in accordance with the control method.

(Initialization) The processor 10 performs initialization so that the state of the cache memory 20 and the contents of the update address storage unit 32 of the cache flash device 30 match before operating the cache flash device 30. In the initialization, all cache blocks are invalidated. The areas A0 to An-1 operate correctly without initialization, but it is desirable in terms of performance that the R pointer and the W pointer corresponding to each area match.

(Normal Operation of Cache Flash Device 30) After the processor 10 performs initialization, the components constituting the cache flash device 30 perform predetermined operations, so that the updated address storage unit 32 Of the dirty block is held. However, when the contents of a certain dirty block are written back to the main memory 51, the addresses held in the areas A0 to An-1 are not deleted correspondingly, and accordingly, the addresses included in the areas A0 to An-1 are not deleted. In some cases, there is no dirty block at the address. It will be described.

When the update address registration unit 33 detects that data has been updated in the cache memory 20, the update address and the processor 10 that has updated the data are updated.
And any one of the areas A0 to An-1 is selected based on the identification number, and an address is to be written in that area.
Here, if there is no empty entry in the area, that is, if the full flag is ON, the entry release unit 36
Stores the contents of the dirty block having the address stored in the entry pointed to by the R pointer in the main memory 51.
A command requesting that data be written back to the system bus 40.
Issue to As a result, if there is a dirty block having the above address, its contents are written back to the main memory 51, and the block is not in the dirty state. If there is no dirty block having the above address, nothing happens. In any case, since this operation can guarantee that there is no dirty block for the address, the vacant entry can be used by the update address registration unit 33 for writing the update address.

When the contents of the dirty block are written back to the main memory 51 in the process of the processor 10 performing data processing, the components constituting the cache flash device 30 do not perform any operation.

(Operation at the time of cache flush by the cache flush unit 30) When the processor 10 commands the cache flush unit 30 to perform a cache flush, the flush execution unit 35 stores it in the update address storage unit 32 based on an instruction from the processor 10. Then, a command is issued to the system bus 40 requesting that the addresses of the dirty blocks having the addresses are sequentially written out and written back to the main memory 51.

As a result, no dirty block exists,
In addition, the process returns to the initial state in which the update address is not stored in the update address storage unit 32.

In the present embodiment, as compared with the first embodiment, the method of setting the area constituting the update address storage unit 32 and the degree of freedom in associating the address with the area are greatly increased. That is, in the first embodiment, the area of the update address storage unit 32 needs to match the configuration of the cache memory 20. This is because there is no means for accurately retaining the address of the dirty block in each area and for writing back the contents of the dirty block to the main memory 51 when the area cannot be fully retained. On the other hand, in the present embodiment, when the update address can no longer be held in the area, the entry release unit 36 fetches one update address held in the area and returns the dirty block having the address. By issuing to the system bus 40 a command requesting that the contents of the cache memory 20 be written back to the main memory 51, the state of the cache memory 20 can be adjusted to the state of the update address storage unit 32.

A description will be given of a method of setting an area constituting the update address storage unit 32 and a specific example of the correspondence between an address and an area.

(Specific Example 1) Consider a case where the cache memory 20 is a direct map system and the number of processors is p. In this case, for example, i of all processors 10
One area can be provided corresponding to the third cache block. Assuming that the number of cache blocks in one cache memory 20 is M, the number n of areas is M.

The number of entries constituting one area is the first
In this embodiment, at least p is necessary, but in the present embodiment, it can be reduced. In this case, the number of cache blocks corresponding to one area is p, but the rate at which a certain cache block is dirty is usually 20.
Since it is about 50%, the number of entries may be about p / 2. Further, there is no particular need for a measure for the write buffer of the processor 10. This will be described later.

(Specific Example 2) Although this is the most extreme example, the number of regions may be one. Since the number of cache blocks is p × M, the number of entries is, for example, p × M / 4
Ｐp × M / 2. At this time, the configuration of the cache memory 20 operates correctly in the direct map system, the set associative system, and the full associative system.

In the case of the present embodiment, the cache flush device 30 does not issue any command to the system bus 40 while there is a free entry. However, when there are no free entries, one command is issued every time a write miss occurs in the cache memory 20 to request writing back the contents of the dirty block to the main memory 51.

Thus, assuming that the number of regions is one,
Although there is an advantage that hardware for selecting a corresponding area from a processor identification number and an update address becomes unnecessary, if a cache miss occurs for the same address several times, the update address is stored in a plurality of entries. The situation is more likely to occur and the performance will be degraded accordingly.

Therefore, when determining the configuration of the update address storage unit 32, it is necessary to match the structure of the cache memory 20 to some extent in consideration of the balance between hardware design and performance.

(Specific Example 3) A case where the cache memory 20 is an N-way set associative system, the number of cache blocks is M, and the number of processors is p will be described. It is assumed that the size of one cache block is B bytes. In this case, the N cache blocks form a group, and the data at the address a is ((a /
B) Mod (M / N)) is stored in the cache block of the (th) group.

At this time, the number of areas is p × M, and the number of entries in each area is 1. Then, the update of the data at address a by the processor with the processor identification number k is (M ×
It corresponds to the (k + (a / BmodM)) th area.

In this method, the cache memory 20 is managed as an N-way set associative, but the cache flash device 30 is managed as a direct map cache memory. As a result,
For example, when the processor 10 having the identification number 0 holds the data at the address 0 in the cache memory 20 in a dirty state and tries to update the data at the address B × M, the cache flash device 30 A command for requesting data to be written back to the main memory 51 is issued.

Although the cache memory 20 of the set associative method is originally managed only in the dirty state and managed by the direct map method, the cache hit rate is deteriorated. By performing management in a map manner, it is only necessary to refer to the update address included in one entry, and hardware simplification and processing speedup can be realized.

In this embodiment, as shown in the specific examples 1 and 2, it is also possible to associate one area with a certain cache block of all the processors 10. Thereby, the update address registration unit 33 and the like
When determining the areas A0 to An-1, the identification number of the processor 10 is not required, so that the present invention can be applied even when the specification of the system bus 40 does not include the processor identification number in the command.

Next, referring to FIG.
Will be described in the case where data D0, D1 and D2 are continuously written at address 0, address B × M, and address 2B × M, respectively. Where B is the size of the cache block, M
Is the number of cache blocks of the processor. The number of entries in the area A0 is two.

(1) The processor 10 attempts to write the data D0 at address 0, but since the data at address 0 is not stored in the cache block 0, the system bus 4
0 requests the main memory 51 or the cache memory 20 of another processor 10 for data from addresses 0 to (B-1), and issues a command to the other processor 10 to update the data to the system bus 40. .

(2) As a result, cache block 0
The data from address 0 to address (B-1) is stored in a dirty state, and the data at address 0 is updated to D0. In the area A0, 0 is stored in correspondence with the update of the address 0. (3) The processor 10 attempts to write the data D1 at the address B × M, but the data at the address B × M is not stored in the cache block 0. A write access request to the main memory 51 for writing data back to the main memory 51 is stored in the write buffer. Also, the main memory 51 or another processor 10 is connected to the system bus 40.
From the B × M address to the (B × M +
B-1) Requests data at the address, and issues a command to the other processor 10 to update the data to the system bus 40.

(4) As a result, cache block 0
The data from the address B × M to the address (B × M + B−1) is stored in a dirty state, and the data at the address B × M is updated to D1. In the area A0, B ×
0 and B × M are stored in correspondence with the update of the address M.

(5) The processor 10 attempts to write the data D2 at the address 2B × M,
Since the data at the address B × M was not stored, a write access request to the main memory 51 for writing back the data at the address B × M currently held in the dirty state to the main memory 51 is sent to the write buffer. Is stored.
As a result, two commands for writing back to the main memory 51 are stored in the write buffer. Further, while requesting data from the address 2B × M to (2B × M + B−1) from the main memory 51 to the system bus 40 or the cache memory 20 of another processor 10, the other processor 10 requests updating of the data. Is issued to the system bus 40.

(6) As a result, cache block 0
The data from address 2B × M to address (2B × M + B−1) is stored in a dirty state, of which 2B × M
The address data is updated to D2. In addition, in the area A0, the 2B × M address is updated in response to the update of the 2B × M address.
There is no empty entry (full flag = ON), so the first stored address 0
Main memory 5 of contents of dirty block having address
1 is a command requesting a write-back to system bus 40.
Issued to

(7) In response to the command issued from the cache flash device 30 to the system bus 40, the main memory 51 of the data at addresses 0 to (B-1) stored in the write buffer of the processor 10 Is written back.

(8) Stored in the write buffer
A command for writing back data from the address B × M to the address (B × M + B−1) to the main memory 51 is issued to the system bus 40.

(9) The cache flush device 30
Since no processing is performed on the command of (8), B × M as well as 2B × M are kept in the entry of the area A0.

(Third Embodiment) Next, a third embodiment of the present invention will be described. FIG. 21 shows a system configuration of a computer system according to the third embodiment of this invention. The configuration of the computer to which the cache flush device 30 is applied is the first
This is the same as in the second embodiment.

The cache flash device 30 includes a bus interface 31, an update address storage unit 32 (area A0).
To An-1), an update address registration unit 33, an update address deletion unit 34, a flash execution unit 35, and an entry release unit 36.

The update address storage unit 32, update address registration unit 33, flash execution unit 35, and entry release unit 36 are the same as those in the second embodiment.

The update address storage unit 32 is similar to the first embodiment. In the first embodiment, an entry that always holds the write-back address is searched for in an area corresponding to the write-back address, and the updated entry is set as an empty entry. Unlike this, in the present embodiment, this process is tried for a certain period of time, and if an entry holding the address is found during that time, it is set as an empty entry. Is closed (do not delete the address). As a result, there is a possibility that an address that is no longer a dirty block may be held in the update address storage unit 32. Therefore, as in the second embodiment, the entry release unit 36 actively creates an empty entry. .

The most typical example in which the update address deletion unit searches for an entry storing the same address as the write-back address for a fixed time will be described with reference to the flowchart shown in FIG. As shown in FIG. 22, the update address deletion unit 34 compares the contents of the entry pointed to by the R pointer with the write-back address (step K3), and if they match, advances the R pointer (steps K5 to K5). K6), delete the update address. As a result,
Since the entry release unit 36 can appropriately reduce the operation of eliminating the dirty block through the flash command issuing unit, the performance can be improved.

Also, instead of the update address deletion unit 34 executing processing for searching for an entry storing the same address as the write-back address for a fixed time, a command indicating data update on the cache memory 20 is sent next. It is also possible to execute this search processing until a command for rewriting the contents of the dirty block back to the main memory 51 is detected until the command is detected. This is more preferable in terms of performance because the frequency of the update address deletion unit 34 actually deleting the update address from the update address storage unit 32 increases.

Further, the update address deletion unit 34 in the present embodiment detects the same address in the update address storage unit 32 upon detecting a command for writing back the contents of the dirty block to the main memory 51. If you decide to delete it. However, for example, when the processor 10 attempts to read data from the cache memory 20 and a cache miss occurs, the detection of a command issued from the cache memory 20 to the system bus 40 triggers the update address storage unit 32
If you find the same address, you can delete it. In general, the detection of a command issued to the system bus 40 and causing the cache memory 20 at the target address to be in a non-dirty state (clean state) can be triggered.
As a result, the frequency at which the update address deletion unit 34 operates increases, the number of times the entry release unit 36 is required decreases, and an improvement in performance can be expected.

(Fourth Embodiment) Next, the fourth embodiment of the present invention will be described.
An embodiment will be described. FIG. 23 shows a system configuration of a computer system according to the fourth embodiment of this invention. The configuration of the computer to which the cache flush device 30 is applied is the same as in the first and second embodiments.

The cache flash device 30 includes a bus interface 31, an update address storage unit 32 (area A0).
To An-1), an update address registration unit 33, an update address deletion unit 34, a flash execution unit 35, and an entry release unit 36.

The update address storage unit 32 includes, in addition to those described in the second embodiment, a dirty block counter which holds the number of dirty blocks corresponding to each area as shown in FIG. Is provided.

The update address registration section 33 has a function of adding +1 to the dirty block counter for the area in addition to the one described in the second embodiment.

The entry release unit 36 is the same as that described in the second embodiment.

FIG. 25 shows a processing flow of the update address registration unit 33 and the entry release unit 36 when the update address registration unit 33 detects a command indicating that data update has occurred in the cache memory 20. When a command indicating data update is detected in step L1, a corresponding area Ai is obtained from the processor identification number and the update address in step L2. At step L3, the dirty block counter is incremented by one. In step L4, it is determined whether or not the full flag of the area Ai is on. If no, step L
If the answer is yes, the entry release unit 36 issues a command requesting the dirty block to be written back to the main memory using the address in the entry indicated by the R pointer of the area Ai in step L5. At step L6, it is determined whether or not the R pointer points to the last entry. If no, the R pointer is incremented by 1 in step L7, and if yes, the R pointer is set to point to the first entry in step L8, and then step L9 is executed. In step L9, the update address is registered at the position indicated by the W pointer.

At step L10, it is determined whether the W pointer points to the last entry. If no, the W pointer is incremented by 1 in step L11, and if yes, the W pointer is pointed to the first entry in step L12, and then step L13 is executed. In Step L13, it is determined whether or not the positions indicated by the W pointer and the R pointer are equal. If they are equal, the full flag is turned on in step L14, and the process ends. If they are not equal, the process ends immediately.

FIG. 26 shows a processing flow of the update address deletion unit 34. Upon detecting a command for writing back the contents of the dirty block to the main memory 51 (step M1), the update address deletion unit 34 determines the address at which the write-back occurred (write-back address) and the processor 10 that has performed the write-back. Based on the identification number, n areas (A0 to An) constituting the update address storage unit 32
-1) is selected (step M2), and its dirty block counter is decremented by one (step M2).
3). As a result, if the value of the dirty block counter becomes zero, the value of the R pointer is made to coincide with the value of the W pointer, and the full flag is turned off (step M5), so that the area is held. Delete all the renewal addresses.

FIG. 27 shows a processing flow of the flash execution unit 35. The flash execution unit 35 includes the processor 10
, A command requesting that the contents of the dirty block having the address stored in each entry be written back to the main memory 51 for an area in which the value of the dirty block counter of each area is not 0 based on the instruction from the system bus 40. (Step N3). Then, when the dirty block counter becomes 0 (step N2), the processing for that area is terminated. In the present embodiment, in addition to the configuration of the second embodiment, a dirty block counter is provided corresponding to each area constituting the update address storage unit 32, and the update address registration unit 33 and the update address deletion unit 34 The above counter is maintained according to the increase or decrease of the dirty block. Then, when all the dirty blocks corresponding to a certain area are gone, the update address deletion unit 34 makes all entries in the area free.

As a result, as compared with the second embodiment, the frequency of activating the entry release unit 36 can be reduced, and the performance of the computer provided with the cache flush device 30 can be improved.

Although the present embodiment has been described as adding means to the second embodiment, the same means can be added to the third embodiment.

In this embodiment, when the update address deletion unit 34 decrements the dirty block counter to 0, all the entries in the corresponding area Ai are vacant. A second use of such a dirty block counter is conceivable.

Now, suppose that the dirty block counter of the area Ai is decremented to 1 as a result. At this time, if the number of update addresses stored in the area Ai (which can be obtained from the difference between the R pointer and the W pointer) is large, for most update addresses held in the area Ai, Dirty blocks mean that they do not exist.

Therefore, if the entry release unit 36 is applied to all entries in the area Ai, the flash execution unit 35 issues a command for writing back to the main memory 51 to an address where a dirty block does not exist. The number of issues can be reduced, and performance can be improved.

As described above, the cache flush devices have been described in the first to fourth embodiments. Next, an embodiment of a fault tolerance computer using any one of the above-described four embodiments will be described.

(Fifth Embodiment) FIG. 28 shows a fifth embodiment of the present invention. The cache flash device 30 according to any one of the first to fourth embodiments is
Connected to. Each processor 10 has a copy-back type cache memory 20 having cache coherency.

The computer of this embodiment always provides one of the following three steps to provide a data processing function with excellent fault tolerance.

(1) Data Processing Step Normal data processing is executed while causing the cache flash device 30 to capture the update address.

(2) Checkpoint Creation Step This step is a step that is periodically executed while temporarily suspending the data processing step. Processor 10
If there are multiple, all the processors 10 execute in synchronization. The processing performed in this step is the following two.

(2a) The context of the processor 10 during data processing (contents of the program counter and general-purpose registers of the processor 10) is stored in the main memory 51.

(2b) The above cache flush device 3
By activating the flash execution unit 35 of 0, the contents of all dirty blocks are written back to the main memory 51.

(3) Rollback & Recovery Step This step is executed when any failure occurs in the computer during execution of the data processing step or the checkpoint creation step. The processing performed in this step is the following two.

(3a) The main memory 51 is restored to the state of the check point created immediately before.

(3b) Data processing is resumed by using the information stored in the restored main memory 51 (when the processing is resumed, the process proceeds to the data processing step).

FIG. 29 shows how the three steps change over time in the computer of this embodiment.

When a predetermined time has elapsed after the start of the data processing step, each processor 10 starts a checkpoint creation step. The first processing performed in the checkpoint creation step is the extent to which the processing has been performed in the immediately preceding data processing step, that is, the context (program counter, state, etc.) of the processor when switching from the immediately preceding data processing step to the checkpoint creation step. Register and general-purpose registers) in the main memory 51. However, in actuality, it may only be stored in the cache memory 20 only. The second process performed in the checkpoint creation step is to write back the contents of the dirty block to the main memory 51. This second processing is
Even when a failure occurs such that the data in the cache memory 20 is destroyed, it is necessary to restart the data processing from the state before the failure by the rollback & recovery step.

When the check point creation step is completed, the data processing step is restarted. At this time, the context of the processor 10 written in the main memory 51 in the checkpoint creation step is used.

FIG. 29 shows that a failure has occurred during the third data processing step, and the rollback & recovery step has started. The first process performed in the rollback & recovery step is to change the state of the main memory 51 to a state in which the immediately preceding checkpoint creation step has been executed, in other words, to a state immediately before the start of the third data processing step. It is to restore.

Generally, in the data processing step, the contents of the dirty blocks are written back to the main memory 51 at any time, so that the state of the main memory 51 slightly changes from the state at the start of the data processing step. Therefore, as a first process of the rollback & recovery step, the state of the main memory 51 is restored to the state at the immediately preceding checkpoint. This restoration method is, for example, each time the contents of the dirty block are written back to the main memory 51, the contents before the writing back of the main memory 51 are stored in the log memory, and the main memory 51 is stored in the log memory. The state of 51 may be restored.

For example, when a write back of data D1 occurs at address a, the main memory controller 50
Suspends the command for writing back, reads out the contents (D0) of the address a of the main memory 51, and then writes D1 at the address a of the main memory 51. Then, a set of the address a and D0 is stored. And rollback &
As a first process of the recovery step, by writing D0 to the main memory 51 at the address a, the state of the main memory 51 at the time of the immediately preceding check point can be restored.

Another method is as follows.
1 is duplicated in the memory A and the memory B, and when the contents of the dirty block are written back to the main memory 51 in the data processing step, only the memory A is written back. Can also be realized by applying the change amount to the memory B.

The second processing in the rollback & recovery step is to restart the data processing step from the restored state of the main memory. This process is the same as the transition from the checkpoint creation step to the data processing step. In the case of the above figure, the fourth data processing step is started from the same state as the third data processing step.

In the rollback & recovery step, the cause of the other failure is examined, and the failed device is disconnected. In the case of a serious failure, the restart of the data processing step is closed and the computer is stopped. Such processing is required. However, since this part is not the gist of the present invention, the description is omitted.

In such a computer, the data processing performance is degraded by the periodic execution of the checkpoint creation step. Therefore, it is important to reduce the time required for the checkpoint creation step. Since most of the processing in the checkpoint creation step is to write back the contents of the dirty block to the main memory 51, the write-back time can be reduced by using the cache flash device 30 of the present invention. It can be expected that the time required for the operation will be greatly reduced.

If the flush execution unit 35 of the cache flush unit 30 is activated in the latter half of the data processing step, the time required for the checkpoint creation step can be further reduced. This is because, by activating the flush execution unit 35 of the cache flush unit 30, the number of dirty blocks at the start of the checkpoint creation step is considerably reduced as compared with the case where the above processing is not performed. If the above processing is not performed, the percentage of dirty blocks is, for example, 30%,
It is about 15%. The flush execution unit 35 of the cache flush device 30 according to the first to fourth embodiments can efficiently retrieve the update address stored in the update address storage unit 32 even when the ratio of dirty blocks is small. Is 15%,
The time required for the checkpoint creation step is almost halved.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described. FIG. 30 shows the configuration of the fault-tolerant computer of this embodiment including any one of the cache flush devices 30 shown in the first to fourth embodiments. FIG.
As shown in FIG. 0, in the present embodiment, the independent first computer 100a and the second computer 100b are connected to the memory update observation unit 60 (within the first computer 100a) and the memory update unit 70.
(Within the second computer 100b). The first computer 100a and the second computer 100b need to include at least the same type of processor 10 and the same type of main memory 51.

The first computer 100a always executes a data processing step and a checkpoint creation step. On the other hand, the second computer 100b normally executes a standby step, and when a failure occurs in the first computer 100a, takes over the data processing that has been executed by the first computer 100a.

The memory update observing section 60 is the first computer 1
By observing the system bus 40 of 00a, the first
The command for updating the main memory 51 generated in the computer 100a is observed and accumulated. Then, the first computer 1
According to the instruction of 00a, the stored command is sent to the memory update unit 70 connected to the second computer 100b. The memory update unit 70 transmits the command received from the memory update observation unit 60 to the system bus 40 of the second computer 100b.
To make the state of the main memory 51 of the second computer 100b coincide with that of the first computer 100a.

The data processing step and the checkpoint creation step of the first computer 100a will be described.

(1) Data Processing Step Normal data processing is executed while causing the cache flash device 30 to capture the update address.

(2) Checkpoint creation step This step is a step that is periodically executed while temporarily suspending the data processing step. Processor 10
If there are multiple, all the processors 10 execute in synchronization. The following three processes are performed in this step.

(2a) The context of the processor 10 during data processing (the contents of the program counter and general-purpose registers of the processor 10) is stored in the main memory 51. (2b) The contents of all dirty blocks are written back to the main memory 51 by activating the flush execution unit 35 of the cache flush device 30.

(2c) For the memory update observation unit 60,
It instructs the stored command to be sent to the memory update unit 70.

In the standby step of the second computer 100b, each processor 10 does not perform data processing, and the memory updating unit 70 determines whether or not a main memory update command from the first computer 100a is periodically received. Find out. If the command is not received for a certain period or more, it is assumed that the first computer 100a has become inoperable, and data processing is performed from the state of the main memory 51 of the second computer 100b at that time.

FIG. 31 shows how the state of the first computer 100a and the state of the second computer 100b change with time in the computer according to the present embodiment.

In the first computer 100a, each processor 10 starts a checkpoint creation step after a predetermined time has elapsed from the start of the data processing step. The first processing performed here is the immediately preceding data processing step.
It is to write in the main memory 51 how far the processing has been performed, that is, the context (contents of the program counter, status register, general-purpose register, etc.) of the processor at the time of switching from the immediately preceding data processing step to the checkpoint creation step. However, in actuality, it may only be stored in the cache memory 20 only.

The second processing performed in the check point creation step is to store the contents of the dirty block in the main memory 5.
Writing back to 1. In the second process, all updates of the main memory 51 in the first computer 100a are performed in the second computer.
Is necessary to send the data to the computer 100b.

The third process performed in the check point creation step is to instruct the memory update observation unit 60 to send the stored command to the memory update unit 70.
This instruction is desirably issued immediately before the checkpoint creation step ends. It is the second computer 10
0b always holds a sound main memory image.

Upon completion of the checkpoint creation step, the data processing step is restarted. At this time, the context of the processor 10 written in the main memory 51 in the checkpoint creation step is used.

FIG. 31 shows that some trouble has occurred during the third data processing step. At this time,
The first computer 100a may simply stop the processing. Alternatively, startup may be performed in preparation for the next occurrence of a failure in the second computer 100b.

The second computer 100b is connected to the first computer 1
The standby step is executed until a failure occurs at 00a. Then, at time T, it is determined that the memory update unit 70 has not received a command from the memory update observation unit 60 for a certain period of time or more, and executes a data processing step. FIG.
In the case of 1, the second computer 100b uses the first computer 1
The data processing step is started from the same state as the third data processing step in 00a.

In such a computer, the data processing performance is degraded by the regular execution of the checkpoint creation step. Therefore, it is important to reduce the time required for the checkpoint creation step. Most of the processing in the checkpoint creation step is to write back the contents of the dirty block back to the main memory 51. Therefore, the use of the cache flush device 30 can greatly reduce the required time.

When the flush execution unit 35 of the cache flush unit 30 is activated in the latter half of the data processing step, the time required for the checkpoint creation step can be further reduced, as in the case of the fifth embodiment. .

The method described in each of the embodiments described above can be executed by a computer as a program such as a magnetic disk (floppy disk, hard disk, etc.), an optical disk (CD-ROM,
It is also possible to write the data on a recording medium such as a DVD or a semiconductor memory and apply it to various devices, or to transmit it via a communication medium and apply it to various devices. A computer that realizes the present apparatus reads the program recorded on the recording medium, and executes the above-described processing by controlling the operation of the program.

[0243]

As described above, according to the present invention, the addresses of all the dirty blocks in the cache memory are
It is stored in any area in the cache flash device. Further, when a certain cache block is once in a dirty state and then no longer in the dirty state, the address is deleted from the area. Then, the flash execution unit sequentially fetches the addresses of the dirty blocks from the respective areas, and issues a command to the system bus to request the contents of the dirty blocks at the addresses to be written back to the main memory. The contents are written back to main memory.

This eliminates the need to perform a process of sequentially determining whether or not all cache blocks are dirty blocks as in a cache flush by conventional software, for example.
A quick and efficient cache flush operation can be performed.

Even when the processor has a write buffer, for example, each area has only one entry, and this entry has not the write buffer but the address (data) stored in the cache block. By storing only the latest update address, an appropriate cache flush operation is ensured.

Further, by providing a mechanism for issuing a write-back request for an update address in accordance with the use status of each area, setting of the number of entries in the area provided in the update address storage unit, association of the area with the address, etc. Greatly expand the degree of freedom.

According to the computer system of the present invention,
Since the cache flush operation, which accounts for most of the checkpoint collection processing, is performed quickly and efficiently, the performance of the entire system is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a structure of an area Ai of an update address storage unit according to the embodiment.

FIG. 3 is an exemplary view showing an operation procedure of an update address registration unit according to the embodiment;

FIG. 4 is a diagram showing an operation procedure of an update address deletion unit according to the embodiment.

FIG. 5 is an exemplary view showing an operation procedure of a flash execution unit according to the embodiment;

FIG. 6 is a view showing an operation procedure of the cache flash device when the update address registration unit according to the embodiment detects a command indicating data update.

FIG. 7 is a diagram showing an operation procedure of the cache flash device when the update address deletion unit according to the embodiment detects a command indicating writing back of a dirty block to the main memory.

FIG. 8 is a block diagram showing a processor according to the embodiment;
Data D0 and D are stored at addresses B × M and 2B × M, respectively.
FIG. 3 is a diagram for explaining an operation when writing data D1 and D2 continuously.

FIG. 9 is a diagram showing a region Ai according to a modification of the embodiment;
FIG.

FIG. 10 is a view showing an operation procedure of the cache flash device when the update address registration unit of the modification example according to the embodiment detects a command indicating data update.

FIG. 11 is a view showing an operation procedure of the cache flash device when the update address deletion unit according to the modification of the embodiment detects a command indicating writing back of a dirty block to the main memory.

FIG. 12 is an exemplary view showing an operation procedure of a flash execution unit of the modification according to the embodiment.

FIG. 13 is an exemplary view for explaining the operation in the case where the processor according to the modification of the embodiment writes data D0, D1, and D2 continuously at addresses 0, B × M, and 2B × M, respectively;

FIG. 14 is an exemplary diagram showing a system configuration of a computer system according to another modification of the embodiment.

FIG. 15 is a diagram showing an operation procedure of the flash execution unit according to the modification of FIG. 14 according to the embodiment;

FIG. 16 is a diagram showing a system configuration of a computer system according to a second embodiment of the present invention.

FIG. 17 is a conceptual diagram showing a configuration of an area of an update address storage unit according to the embodiment;

FIG. 18 is a processing flowchart of the update address registration unit and the entry release unit when the update address registration unit detects a command indicating that data update has occurred in the cache memory according to the embodiment.

FIG. 19 is a flowchart of a process performed by a flash execution unit according to the embodiment;

FIG. 20 is a block diagram showing a processor according to the embodiment which stores data D0, D0 at address 0, B × M, and 2B × M, respectively;
FIG. 8 is a diagram for explaining an operation when writing D1 and D2 continuously.

FIG. 21 is a diagram showing a system configuration of a computer system according to a third embodiment of the present invention.

FIG. 22 is a diagram illustrating an example in which the update address deletion unit searches for an entry in which the same address as the write-back address is stored for a certain period of time according to the embodiment;

FIG. 23 is a diagram showing a system configuration of a computer system according to a fourth embodiment of the present invention.

FIG. 24 is a conceptual diagram showing a configuration of an area of an update address storage unit according to the embodiment.

FIG. 25 is a flowchart of processing performed by the update address registration unit and the entry release unit when the update address registration unit detects a command indicating that data update has occurred in the cache memory according to the embodiment;

FIG. 26 is a flowchart showing processing of an update address deletion unit according to the embodiment.

FIG. 27 is a flowchart showing processing of a flash execution unit according to the embodiment;

FIG. 28 is a diagram showing a configuration of a fault-tolerant computer according to a fifth embodiment of the present invention.

FIG. 29 is a view showing a state where three steps change over time in the computer according to the embodiment.

FIG. 30 is a diagram showing a configuration of a fault tolerance computer according to a sixth embodiment of the present invention.

FIG. 31 shows a first computer 100a and a second computer 1 over time in the computer according to the embodiment.
The figure showing a mode that the state of 00b changes.

FIG. 32 is a diagram showing a program for performing a conventional cache flush operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Processor 20 ... Cache memory 30 ... Cache flash device 31 ... Bus interface 32 ... Update address storage part 33 ... Update address registration part 34 ... Update address deletion part 35 ... Flash execution part 36 ... Entry release part 37 ... Update address reading part 40 system bus 50 memory controller 51 main memory 100a first computer 200b second computer

Claims (76)

[Claims] 1. A system comprising: at least one processor having a copy-back type cache memory having a bus snoop mechanism; a main memory; and a system bus connecting the at least one processor and the main memory. A cache flash device used in a computer, wherein an address of data held by a dirty block which is a cache block in a state of holding data to be written back to the main memory among cache blocks secured in the cache memory. Update address storage means having a plurality of areas for storing data, and detecting the data update on the cache memory by monitoring the system bus, and performing the update with the update address at which the data has been updated. Based on the processor identification number An update address registering means for selecting any one of the areas of the update address storage means and storing the update address in the selected area; and A write-back of the retained data to the main memory is detected, and based on the write-back address at which the data was written back and the identification number of the processor that performed the write-back, each area of the update address storage means is rewritten. Update address deletion means for selecting any one of the areas and deleting an update address that matches the write-back address stored in the selected area; and storing the update address in response to an instruction from the processor. Means for sequentially reading out all update addresses stored in the means, and reading the update address indicated by the read update address. A flash execution unit for issuing to the system bus a command for requesting writing back of data held by the security lock to the main memory. 2. A copy-back type direct-mapped cache memory having a bus snoop mechanism and at least one processor, a main memory, and a system bus connecting the at least one processor and the main memory. A cache flash device used in a computer comprising: a cache block provided corresponding to each cache block secured in the cache memory and holding data to be written back to the main memory. Update address storage means for storing an address of data held by a certain dirty block, wherein the update address storage means comprises a plurality of areas each having one entry; and Updating data in memory Based on the detected address and the update address at which the data was updated, and the identification number of the processor that has performed the data update, any one of the areas of the update address storage means is selected, and the selected area is assigned to the selected area. Update address registering means for storing the update address; monitoring the system bus to detect write-back of the data held by the dirty block to the main memory; Based on the identification number of the processor that has returned, one of the areas of the update address storage means is selected, and the update address stored in the selected area is compared with the write-back address. Update address deletion means for deleting an update address stored in the selected area when the two coincide with each other; In response to an instruction from the processor, all update addresses stored in the update address storage means are sequentially read, and data stored in the dirty block indicated by the read update address is written back to the main memory. Flash execution means for issuing a command for requesting a command to the system bus. 3. A copy-back type direct-mapped cache memory having a bus snoop mechanism and at least one processor, a main memory, and a system bus connecting the at least one processor and the main memory. A cache flash device used in a computer comprising: a cache block provided corresponding to each cache block secured in the cache memory and holding data to be written back to the main memory. Update address storage means for storing an address of data held by a certain dirty block, each area having one entry, and a plurality of counters provided corresponding to this area; Monitoring the above system bus Detecting the data update on the cache memory, and based on the update address at which the data update has been performed and the identification number of the processor that has performed the data update, the data in the plurality of areas provided in the update address storage means. An update address registering means for selecting one of the areas, storing the update address in the selected area, and incrementing the counter corresponding to the area, and holding the dirty block by monitoring the system bus The write-back of the data to be written to the main memory is detected, and based on the write-back address at which the write-back has been performed and the identification number of the processor that has performed the write-back, each area of the update address storage means is Select any area and decrement the counter corresponding to the selected area A new address deleting unit, and sequentially reading an update address stored in an area where the value of the counter corresponding to the area is not an initial value in each area of the update address storage means in response to an instruction from the processor. Flash execution means for issuing to the system bus a command requesting a write-back of the data held by the dirty block indicated by the read update address to the main memory. . 4. A system comprising: at least one processor having a copy-back type cache memory having a bus snoop mechanism; a main memory; and a system bus connecting the at least one processor and the main memory. An address of data held by a dirty block, which is a cache block in a state of holding data to be written back to the main memory among cache blocks secured in the cache memory, the cache flash device being used in a computer. Update address storage means having a plurality of areas for storing the data, and detecting the data update on the cache memory by monitoring the system bus, and performing the update with the update address where the data has been updated. Based on the processor identification number An update address registering means for selecting any one of the areas of the update address storage means and storing the update address in the selected area; and A write-back of the retained data to the main memory is detected, and based on the write-back address at which the data was written back and the identification number of the processor that performed the write-back, the update address storage means Update address deletion means for selecting any one of the areas and deleting an update address that matches the write-back address stored in the selected area; and updating all the update addresses stored in the update address storage means. Sequential reading, update address prepared so that the above-mentioned processor can sequentially read the read update address And a cache read device. 5. A copy-back type direct-mapped cache memory having a bus snoop mechanism and at least one processor, a main memory, and a system bus connecting the at least one processor and the main memory. A cache flash device used in a computer comprising: a cache block provided corresponding to each cache block secured in the cache memory and holding data to be written back to the main memory. Update address storage means for storing an address of data held by a certain dirty block, wherein the update address storage means comprises a plurality of areas each having one entry; and Updating data in memory Based on the detected address and the update address at which the data was updated, and the identification number of the processor that has performed the data update, any one of the areas of the update address storage means is selected, and the selected area is assigned to the selected area. Update address registering means for storing the update address; monitoring the system bus to detect write-back of the data held by the dirty block to the main memory; Based on the returned identification number of the processor, any one of the areas of the update address storage means is selected, and the update address stored in the selected area and the write-back address are determined. Comparing, and when they match, update address deletion means for deleting the update address stored in the selected area. The update address reading all updates address stored in the storage means sequentially, the cache flush apparatus characterized by the update address thus read out to and a update address reading means for preparing to let out sequentially to read the processor. 6. A copy-back type direct-mapped cache memory having a bus snoop mechanism and at least one processor, a main memory, and a system bus connecting the at least one processor and the main memory. A cache flash device used in a computer comprising: a cache block provided corresponding to each cache block secured in the cache memory and holding data to be written back to the main memory. Update address storage means for storing an address of data held by a certain dirty block, each area having one entry, and a plurality of counters provided corresponding to this area; Monitoring the above system bus The data update on the cache memory is detected, and based on the update address at which the data has been updated and the identification number of the processor that has performed the data update, any one of the areas in the update address storage means is detected. Selecting an area, storing the update address in the selected area, incrementing the counter corresponding to the area, and updating address registration means; and monitoring the system bus to store the data held by the dirty block. A write-back to the main memory is detected, and based on a write-back address at which the write-back has been performed and an identification number of the processor that has performed the write-back, any one of the areas of the update address storage means is determined. An update address that selects an area and decrements the counter corresponding to the selected area Deleting means; sequentially reading out update addresses stored in an area in which the counter value corresponding to the area is not an initial value among the areas provided in the update address storage means, and the processor sequentially reading the read update addresses. A cache flash device comprising: an update address reading means prepared so as to be issued. 7. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. An address of data held by a dirty block, which is a cache block in a state of holding data to be written back to the main memory among cache blocks secured in the cache memory, the cache flash device being used in a computer. Update address storage means having a plurality of areas for storing the data, and detecting the data update on the cache memory by monitoring the system bus, and performing the update with the update address where the data has been updated. Based on the processor identification number Update address registration means for selecting one of the areas of the update address storage means and storing the update address in the selected area; and a free entry of the area selected by the update address registration means. The number is compared with a predetermined value, and when the number of empty entries falls below the predetermined value, one of the update addresses already stored in the area is selected, and the selected update address indicated by the selected update address is selected. An entry release means for issuing to the system bus a command requesting a write-back of the data held by the dirty block to the main memory, and setting the entry storing the updated address to a free entry; In response to the instruction, sequentially read all update addresses stored in the update address storage means, A flash execution unit for issuing, to the system bus, a command requesting a write-back of the data held by the dirty block indicated by the read update address to the main memory. 8. The cache memory is of an n-way set associative type, and each of a plurality of areas provided in the update address storage means has a one-to-one correspondence with a group formed by n cache blocks. 8. A device according to claim 7, wherein
A cache flush device as described. 9. A system comprising: at least one processor having a copy-back type cache memory having a bus snoop mechanism; a main memory; and a system bus connecting the at least one processor and the main memory. An address of data held by a dirty block, which is a cache block in a state of holding data to be written back to the main memory among cache blocks secured in the cache memory, the cache flash device being used in a computer. Update address storage means having a plurality of areas for storing the data, and detecting the data update on the cache memory by monitoring the system bus, and performing the update with the update address where the data has been updated. Based on the processor identification number An update address registering means for selecting any one of the areas of the update address storage means and storing the update address in the selected area; and A write-back of the retained data to the main memory is detected, and based on the write-back address at which the write-back has been performed and the identification number of the processor that has performed the write-back, each of the update address storage means If any area is selected, a search is performed for a fixed time to determine whether or not there is an update address that matches the write-back address in the selected area, and if an update address that matches the write-back address is detected, Update address deletion means for deleting the update address; and the number of empty entries in the area selected by the update address registration means. When the number of vacant entries is smaller than the predetermined value, one of the update addresses already stored in the area is selected, and the dirty block indicated by the selected update address is selected. A command for requesting writing back of the retained data to the main memory is issued to the system bus, and entry release means for setting the entry storing the updated address to a free entry; and responding to an instruction from the processor. Then, all the update addresses stored in the update address storage means are sequentially read, and a command requesting writing back of the data held by the dirty block indicated by the read update address to the main memory is executed by the system. Flash execution means for issuing to a bus. Flash flush device. 10. The update address deletion means, when detecting a command indicating that all cache blocks holding data indicated by a certain address are not dirty blocks, reads from the address an address of each area of the update address storage means. 10. The method according to claim 9, wherein any one of the areas is selected, and when the selected area is searched and an update address that matches the write-back address is detected, the update address is deleted. Cache flush device. 11. A system comprising: at least one processor having a copy-back type cache memory having a bus snoop mechanism; a main memory; and a system bus connecting the at least one processor and the main memory. An address of data held by a dirty block, which is a cache block in a state of holding data to be written back to the main memory among cache blocks secured in the cache memory, the cache flash device being used in a computer. Update address storage means having a plurality of areas for storing the data, and detecting the data update on the cache memory by monitoring the system bus, and performing the update with the update address where the data has been updated. Processor identification number Then, any one of the areas of the update address storage means is selected, the update address registration means for storing the update address in the selected area, and the dirty block is monitored by monitoring the system bus. The write-back of the data held in the main memory is detected, and based on the write-back address at which the write-back has been performed and the identification number of the processor that has performed the write-back, the contents of each area of the update address storage means are determined. Is searched until there is an update address in the selected area that matches the write-back address until the cache flash device detects a command to be processed next. Update address deletion means for deleting the update address when an update address matching the return address is detected; The number of free entries in the area selected by the update address registering means is compared with a predetermined value, and when the number of free entries falls below the predetermined value, any one of the update addresses already stored in the area is replaced. A command is issued to the system bus requesting that the data held by the dirty block indicated by the selected update address be written back to the main memory, and the entry storing the update address be freed. An entry release unit to be an entry; and sequentially reading all update addresses stored in the update address storage unit in response to an instruction from the processor, and data held by the dirty block indicated by the read update address. A command requesting write back to the main memory A cache flush device comprising: a flush execution unit for issuing. 12. The update address deletion means, when detecting a command indicating that all the cache blocks holding data indicated by a certain address are not dirty blocks, reads from the address an address of each area of the update address storage means. 12. The method according to claim 11, wherein any one of the selected areas is selected, and if the updated address matching the write-back address is detected by searching the selected area, the updated address is deleted. Cache flush device. 13. The cache flash device according to claim 7, wherein the number of entries in each of the plurality of areas included in said update address storage means is smaller than the number of corresponding cache blocks. 14. The cache flash device according to claim 9, wherein the number of entries in each of the plurality of areas included in said update address storage means is smaller than the number of corresponding cache blocks. 15. The cache flash device according to claim 11, wherein the number of entries in each of the plurality of areas included in said update address storage means is smaller than the number of corresponding cache blocks. 16. The cache flash device according to claim 1, wherein a plurality of areas provided in said update address storage means can be selected only by said update address. 17. The cache flash device according to claim 7, wherein a plurality of areas provided in said update address storage means can be selected only by said update address. 18. The cache flash device according to claim 9, wherein a plurality of areas provided in said update address storage means can be selected only by said update address. 19. The cache flash device according to claim 11, wherein a plurality of areas provided in said update address storage means can be selected only by said update address. 20. The update address storage means has a dirty block counter for storing the number of the dirty blocks corresponding to each area for storing the address of the data stored in the dirty block. The address registering means has an incrementing means for incrementing the dirty block counter corresponding to the selected area, and detects writing back of the data held by the dirty block to the main memory by monitoring the system bus, Any one of the areas of the update address storage means is selected from the write-back address and the identification number of the processor that has performed the write-back, and the dirty block counter corresponding to the selected area is decremented. Decrement means and this When the dirty block counter becomes an initial value due to the decrement by the decrementing means, the entry block releasing means for setting all the entries storing the update addresses in the area corresponding to the dirty block counter to empty entries is provided. 8. The cache flush device according to claim 7, wherein: 21. The update address storage means includes a dirty block counter for storing the number of the dirty blocks corresponding to each area for storing the address of the data held by the dirty block, The address registration means has increment means for incrementing the dirty block counter corresponding to the selected area, and the update address deletion means has decrement means for decrementing the dirty block counter corresponding to the selected area. When the dirty block counter becomes an initial value by the decrement of the decrementing means, a batch deleting means for deleting all update addresses stored in an area corresponding to the dirty block counter is provided. The cache flush device according to claim 9. 22. The update address storage means includes a dirty block counter for storing the number of the dirty blocks corresponding to respective areas for storing addresses of data held by the dirty blocks, The address registration means has increment means for incrementing the dirty block counter corresponding to the selected area, and the update address deletion means has decrement means for decrementing the dirty block counter corresponding to the selected area. When the dirty block counter becomes an initial value by the decrement of the decrementing means, a batch deleting means for deleting all update addresses stored in an area corresponding to the dirty block counter is provided. The cache flush device according to claim 11. 23. The entry release means, wherein the number of update addresses stored in any one of the plurality of areas provided in the update address storage means determines whether the number of update addresses of the dirty block counter corresponding to the area is equal to the number of update addresses. When the value increases beyond a predetermined value, one of the update addresses already stored in the area is selected, and the dirty block indicated by the selected update address is held. 21. The cache flash device according to claim 20, wherein a command requesting a write-back of the data to be written back to the main memory is issued to the system bus, and the entry storing the updated address is made an empty entry. . 24. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. A cache system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 1; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing a data processing context synchronously executed by all the processors in the main memory and data held by all dirty blocks executed by the flush execution means of the cache flash device. Main memory above Checkpoint creation means including writing back to the main memory, and when a failure occurs, restoring the main memory at the time of the checkpoint taken immediately before, and using the information held in the restored main memory, A computer system comprising: rollback recovery means for restarting processing. 25. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 3. A computer system for periodically taking a checkpoint for restarting an interrupted process, comprising: a cache flush device according to claim 2; and a normal data process while causing the cache flush device to capture an update address. Data processing means to be executed, storing of a context during data processing executed by all of the processors synchronously in the main memory, and data storage of all dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back; and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. A computer system comprising: a rollback recovery unit for restarting. 26. A system comprising at least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 4. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 3; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed by all of the processors synchronously, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back; and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. A computer system comprising: a rollback recovery unit for restarting. 27. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 8. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 7; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back; and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. A computer system comprising: a rollback recovery unit for restarting. 28. At least one processor having a copy-back type cache memory having a bus snooping mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 9. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 8; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back; and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. A computer system comprising: a rollback recovery unit for restarting. 29. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 10. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 9; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back; and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. A computer system comprising: a rollback recovery unit for restarting. 30. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 11. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 10; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 31. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 12. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 11; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 32. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 13. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 12; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 33. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 14. A computer system for periodically taking a checkpoint for restarting an interrupted process, comprising: a cache flush device according to claim 13; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing a data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing a flush operation of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 34. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 15. A computer system for periodically taking a checkpoint for restarting an interrupted process, comprising: a cache flush device according to claim 14; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 35. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 16. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 15; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 36. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 17. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 16; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 37. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 18. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 17; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 38. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 19. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 18; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 39. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 20. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 19; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 40. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 21. A computer system for periodically taking a checkpoint for restarting an interrupted process, comprising: a cache flush device according to claim 20; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 41. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 22. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 21; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing a data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing a flush operation of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 42. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 23. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 22; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing the data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing the data stored in all the dirty blocks executed by the flash execution means of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 43. At least one processor having a copy-back type cache memory having a bus snooping mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 24. A computer system for periodically taking a checkpoint for restarting an interrupted process, comprising: a cache flush device according to claim 23; and normal data processing while causing the cache flush device to capture an update address. And a data processing means for executing a data processing context which is executed synchronously by all of the processors, storing the context in the main memory, and executing a flush operation of the cache flash device. To the above main memory Checkpoint creation means including write-back of the main memory, and, when a failure occurs, restoring the main memory at the time of the immediately preceding checkpoint, and performing data processing using the restored information held in the main memory. Computer system comprising: a rollback recovery unit for restarting the process. 44. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 5. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 4; and normal data processing while causing the cache flush device to capture an update address. Data processing means for executing the processing, and storing the context during the data processing executed by all of the processors in synchronization with the main memory and acquiring the update address via the update address reading means of the cache flash device, Indicated by the acquired update address Checkpoint creation means including writing back all the dirty blocks to the main memory by executing an instruction sequence for writing back the data to be written from the cache memory to the main memory; Rollback recovery means for restoring the main memory at the time of the immediately preceding checkpoint, and resuming data processing using the information retained in the restored main memory. Computer system. 45. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 6. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 5; and normal data processing while causing the cache flush device to capture an update address. And a data processing unit that executes the processing, storing the context during the data processing executed by all of the processors in synchronization with the main memory and acquiring the update address through the update address reading unit of the cache flash device, Indicated by the acquired update address The checkpoint creation means including writing back the data held by all the dirty blocks to the main memory by executing an instruction sequence for writing back the data to be written from the cache memory to the main memory; Rollback recovery means for restoring the main memory at the time of a checkpoint taken immediately before when the occurrence occurs, and resuming data processing using the information retained in the restored main memory. Characteristic computer system. 46. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. 7. A computer system for periodically collecting checkpoints for restarting interrupted processing, comprising: a cache flush device according to claim 6; and normal data processing while causing the cache flush device to capture an update address. And a data processing unit that executes the processing, storing the context during the data processing executed by all of the processors in synchronization with the main memory and acquiring the update address through the update address reading unit of the cache flash device, Indicated by the acquired update address The checkpoint creation means including writing back the data held by all the dirty blocks to the main memory by executing an instruction sequence for writing back the data to be written from the cache memory to the main memory; Rollback recovery means for restoring the main memory at the time of a checkpoint taken immediately before when the occurrence occurs, and resuming data processing using the information retained in the restored main memory. Characteristic computer system. 47. At least a first computer and a second computer, and a command for writing to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. A memory update observing unit that transmits a command to the second computer; and a command that receives the command transmitted by the memory update observing unit and writes the same in the main memory of the second computer in the same manner as the first computer. Memory updating means for issuing a command,
A computer system for periodically taking a checkpoint for restarting an interrupted process, wherein the first computer acquires a cache flush device according to claim 1 and captures an update address in the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors in synchronization with the main memory; and all dirty processing executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means Serial when no command is received from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 48. At least a first computer and a second computer, and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. A memory update observing unit for transmitting a command to the second computer; receiving the command transmitted by the memory update observing unit, and transmitting the command to the main memory of the second computer;
And a memory updating means for issuing a write command similar to that of the first computer, wherein the first computer periodically obtains a checkpoint for restarting the interrupted process. A cache flush device described above; data processing means for executing normal data processing while causing the cache flush device to capture an update address; and Storing, writing back the data held by all the dirty blocks executed by the flush execution unit of the cache flush unit to the main memory, and transmitting the stored command to the memory update observation unit to the second computer. Checkpoint collection means including transmission instructions The second computer includes a standby unit that starts data processing when the memory update unit has not received a command from the memory update observation unit for a predetermined time. Computer system. 49. At least a first computer and a second computer, and a command for writing to a main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires the cache address of the cache flush device according to claim 3 and the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors synchronously in the main memory; and all dirty operations executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means Serial when no command is received from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 50. At least first and second computers and a write command to the main memory generated by the first computer are captured and accumulated, and when instructed by the first computer, the accumulated commands are stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
A computer system for periodically collecting a checkpoint for restarting an interrupted process, wherein the first computer acquires the cache address of the cache flush device according to claim 7 and an update address of the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors synchronously in the main memory; and all dirty operations executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means Serial when no command is received from the memory update monitoring means, the computer system characterized by comprising comprises a waiting means for starting the data processing. 51. At least a first and a second computer, and a write command to a main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires the cache address of the cache flush device according to claim 8 and an update address of the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors synchronously in the main memory; and all dirty operations executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means Serial when no command is received from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 52. At least a first computer and a second computer, and a command for writing to a main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored commands are stored. A memory update observing unit for transmitting a command to the second computer; receiving the command transmitted by the memory update observing unit, and transmitting the command to the main memory of the second computer;
A computer updating means for issuing a write command similar to that of the computer, and periodically collecting checkpoints for restarting the interrupted processing, wherein the first computer comprises: A cache flush device described above; data processing means for executing normal data processing while causing the cache flush device to capture an update address; and Storing, writing back the data held by all the dirty blocks executed by the flush execution unit of the cache flush unit to the main memory, and transmitting the stored command to the memory update observation unit to the second computer. Checkpoint collection means including transmission instructions The second computer further comprises a standby unit for starting data processing when the memory update unit has not received a command from the memory update observation unit for a predetermined time. Computer system. 53. At least first and second computers and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored commands are stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
A computer system for periodically taking a checkpoint for restarting an interrupted process, wherein the first computer acquires a cache flush device according to claim 10 and captures an update address in the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors synchronously in the main memory; and all dirty operations executed by the flash executing means of the cache flash device. A checkpoint collection unit including a write-back of data held by the block to the main memory, and a transmission instruction to the memory update observation unit for transmitting the stored command to the second computer. Means that the memory updating means When it does not receive a command from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 54. At least first and second computers, and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored commands are stored. A memory update observing unit that transmits a command to the second computer; and a command that receives the command transmitted by the memory update observing unit and writes the same in the main memory of the second computer in the same manner as the first computer. Memory updating means for issuing a command,
12. A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires the cache address of the cache flush device according to claim 11 and an update address of the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors in synchronization with the main memory; and all dirty processing executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means exceeds a predetermined time. When it does not receive a command from said memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 55. At least a first computer and a second computer, and a command for writing to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; Memory updating means for issuing a command,
A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires the cache address of the cache flush device according to claim 12 and an update address of the cache flush device. Data processing means for executing normal data processing while storing the context during the data processing which is executed by all of the processors in synchronization with the main memory; A checkpoint collection unit including a write-back of data held by the block to the main memory, and a transmission instruction to the memory update observation unit for transmitting the stored command to the second computer. Means that the memory updating means When it does not receive a command from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 56. At least first and second computers and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored commands are stored. A memory update observing unit that transmits a command to the second computer; and a command that receives the command transmitted by the memory update observing unit and writes the same in the main memory of the second computer in the same manner as the first computer. Memory updating means for issuing a command,
14. A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires a cache flush device according to claim 13 and an update address in the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors in synchronization with the main memory; and all dirty processing executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means exceeds a predetermined time. When it does not receive a command from said memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 57. At least first and second computers and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. A memory update observing unit that transmits a command to the second computer; and a command that receives the command transmitted by the memory update observing unit and writes the same in the main memory of the second computer in the same manner as the first computer. Memory updating means for issuing a command,
A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires the cache address of the cache flush device according to claim 14 and an update address of the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors in synchronization with the main memory; and all dirty processing executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means exceeds a predetermined time. When it does not receive a command from said memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 58. At least first and second computers, and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
16. A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires the cache address of the cache flush device according to claim 15 and the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors synchronously in the main memory; and all dirty operations executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means exceeds a predetermined time. When it does not receive a command from said memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 59. At least first and second computers, and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
17. A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires a cache flush device according to claim 16 and an update address in the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors synchronously in the main memory; and all dirty operations executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means exceeds a predetermined time. When it does not receive a command from said memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 60. At least a first computer and a second computer, and a write command to a main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. A memory update observing unit that transmits a command to the second computer; and a command that receives the command transmitted by the memory update observing unit and writes the same in the main memory of the second computer in the same manner as the first computer. Memory updating means for issuing a command,
A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer acquires the cache address of the cache flush device according to claim 17 and the cache flush device. Data processing means for executing normal data processing while storing the context during data processing which is executed by all of the processors in synchronization with the main memory; and all dirty processing executed by the flash executing means of the cache flash device. A write-back of the data held by the block to the main memory; and a checkpoint collection unit including an instruction to transmit the stored command to the memory update observation unit to the second computer. The computer may be configured such that the memory updating means exceeds a predetermined time. When it does not receive a command from said memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 61. At least a first computer and a second computer, and a command for writing to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. A memory update observing unit that transmits a command to the second computer; and a command that receives the command transmitted by the memory update observing unit and writes the same in the main memory of the second computer in the same manner as the first computer. Memory updating means for issuing a command,
A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer causes the cache flush device according to claim 18 to acquire an update address. Data processing means for executing normal data processing while storing contexts in the main memory for data processing contexts executed synchronously by all of the processors, and all dirty blocks executed by the flush execution means of the cache flush device And a checkpoint collecting means including an instruction to write back the data held in the main memory to the main memory, and to transmit the stored command to the memory update observing means to the second computer. Means that the memory updating means When it does not receive a command from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 62. At least first and second computers, and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. A memory update observing unit that transmits a command to the second computer; and a command that receives the command transmitted by the memory update observing unit and writes the same in the main memory of the second computer in the same manner as the first computer. Memory updating means for issuing a command,
20. A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer causes the cache flush device according to claim 19 to capture an update address. Data processing means for executing normal data processing while storing contexts in the main memory for data processing contexts executed synchronously by all of the processors, and all dirty blocks executed by the flush execution means of the cache flush device And a checkpoint collecting means including an instruction to write back the data held in the main memory to the main memory, and to transmit the stored command to the memory update observing means to the second computer. Means that the memory updating means When it does not receive a command from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 63. At least first and second computers and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored commands are stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
21. A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer causes the cache flash device according to claim 20 to capture an update address. Data processing means for executing normal data processing while storing all contexts during data processing which are executed synchronously by the processors in the main memory, and all dirty blocks executed by the flash execution means of the cache flash device And a checkpoint collecting means including an instruction to write back the data held in the main memory to the main memory, and to transmit the stored command to the memory update observing means to the second computer. Means that the memory updating means When it does not receive a command from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 64. At least first and second computers, and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. A memory update observing unit that transmits a command to the second computer; and a command that receives the command transmitted by the memory update observing unit and writes the same in the main memory of the second computer in the same manner as the first computer. 22. A computer system comprising: a memory updating unit for issuing a command; and periodically collecting checkpoints for restarting the interrupted processing, wherein the first computer comprises: a cache flush device according to claim 21; Data processing means for executing normal data processing while causing the cache flash device to capture an update address; Storing in the main memory the context in which data is being processed, all executed synchronously, writing back to the main memory the data held by all the dirty blocks executed by the flush execution means of the cache flash device, and Checkpoint collection means including an instruction to transmit the stored command to the second computer to the memory update observation means, the second computer comprising: A computer system comprising a standby unit for starting data processing when a command is not received from an update observation unit. 65. At least first and second computers and a write command to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored data is stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer causes the cache flush device according to claim 22 to capture an update address. Data processing means for executing normal data processing while storing all contexts during data processing which are executed synchronously by the processors in the main memory, and all dirty blocks executed by the flash execution means of the cache flash device And a checkpoint collecting means including an instruction to write back the data held in the main memory to the main memory, and to transmit the stored command to the memory update observing means to the second computer. Means that the memory updating means When it does not receive a command from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 66. At least a first computer and a second computer, and a command for writing to the main memory generated by the first computer are captured and stored, and when instructed by the first computer, the stored commands are stored. Memory update observing means for transmitting a command to the second computer; receiving the command transmitted by the memory update observing means; and writing the same in the main memory of the second computer as in the first computer. Memory updating means for issuing a command,
A computer system for periodically collecting checkpoints for restarting interrupted processing, wherein the first computer causes the cache flash device of claim 23 to capture an update address. Data processing means for executing normal data processing while storing all contexts during data processing which are executed synchronously by the processors in the main memory, and all dirty blocks executed by the flash execution means of the cache flash device And a checkpoint collecting means including an instruction to write back the data held in the main memory to the main memory, and to transmit the stored command to the memory update observing means to the second computer. Means that the memory updating means When it does not receive a command from the memory update monitoring means, computer system, characterized by comprising standby means for initiating a data processing. 67. The method according to claim 24, wherein said data processing means includes a process of activating said flush execution means of said cache flush device. Computer system. 68. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. A cache flash device which is used in a computer and has update address storage means provided with a plurality of areas for storing addresses of data held by a dirty block which is a cache block holding data to be written back to the main memory. A storage medium storing a program for controlling the data processing, wherein the processor detects the data update on the cache memory by monitoring the system bus, and updates the updated address of the data and the data updated. On the basis of the identification number and Selecting one of the areas of the update address storage means from the cache blocks secured in the cache memory and storing the update address in the selected area; and monitoring the system bus By doing so, the writing back of the data held by the dirty block to the main memory is detected, and the update is performed based on the write back address at which the data was written back and the identification number of the processor that performed the writing back. A step of selecting any one of the areas of the address storage means and deleting an update address that matches the write-back address stored in the selected area; and, in response to an instruction from the processor, Sequentially reading out all update addresses stored in the update address storage means, Issuing a command requesting write-back of data held by the dirty block to the main memory to the main memory, to the system bus. 69. At least one processor provided with a copy-back type direct-mapped cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. Dirty blocks, which are used in a computer provided and are provided corresponding to each of the cache blocks secured in the cache memory and are cache blocks in a state where data to be written back to the main memory are retained. A storage medium for storing a program for controlling a cache flash device having an update address storage unit provided with a plurality of areas each having one entry, the area being for storing data addresses. Monitor the above system bus The data update on the cache memory is thereby detected, and based on the update address at which the data was updated and the identification number of the processor that performed the data update, Selecting the area and storing the update address in the selected area; and monitoring the system bus to detect writing back of the data held by the dirty block to the main memory and writing the data. Based on the restored write-back address and the identification number of the processor that performed the write-back, any one of the areas of the update address storage means is selected, and the update stored in the selected area is selected. The address is compared with the write-back address, and when they match, the update address stored in the selected area is And sequentially reading all update addresses stored in the update address storage means in response to an instruction from the processor, and reading the main data of the data held by the dirty block indicated by the read update address. Issuing a command requesting a write-back to the memory to the system bus. 70. At least one processor having a copy-back type and direct-mapped cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. A dirty block, which is used in a computer provided and is provided corresponding to each cache block secured in the cache memory and is a cache block in a state of holding data to be written back to the main memory, is held. A cache flash device is provided which has an area for storing data addresses, each area having one entry, and an update address storage means having a plurality of counters provided corresponding to this area. Program for recording A recording medium, detecting data update in the cache memory by monitoring the system bus, and based on an update address at which data is updated and an identification number of the processor that has performed data update, A step of selecting any one of a plurality of areas provided in the update address storage means, storing the update address in the selected area, and incrementing the counter corresponding to the area; By monitoring the write-back of the data held by the dirty block to the main memory, and based on the write-back address where the write-back was performed and the identification number of the processor that performed the write-back, Select any one of the areas of the update address storage means and correspond to the selected area Decrementing the counter, and, in response to an instruction from the processor, an update address stored in an area where the value of the counter corresponding to the area is not an initial value in each area of the update address storage means. And a procedure for issuing to the system bus a command for requesting the main memory to write back the data held by the dirty block indicated by the read update address. Recording medium. 71. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. An area for storing an address of data held by a dirty block, which is used in a computer and is a cache block in a state of holding data to be written back to the main memory among cache blocks secured in the cache memory. A storage medium storing a program for controlling a cache flash device having an update address storage means provided with a plurality of data storage means, wherein a data update in the cache memory is detected by monitoring the system bus, and the data update is performed. There was an update address and A step of selecting any one of the areas of the update address storage means based on the identification number of the processor that has performed the data update, and storing the update address in the selected area; By monitoring the system bus, write-back of the data held by the dirty block to the main memory is detected, and based on the write-back address where the data was written back and the identification number of the processor that performed the write-back. Selecting one of the areas in the update address storage means and deleting the update address that matches the write-back address stored in the selected area; All stored update addresses are sequentially read, and the read update addresses are sequentially read by the processor. And a computer-readable recording medium on which a program for executing the steps of: 72. At least one processor having a copy-back type direct-mapped cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. A dirty block, which is used in a computer provided with the cache block and is provided corresponding to each of the cache blocks secured in the cache memory and is a cache block in a state in which data to be written back to the main memory is retained. A storage medium for storing a program for controlling a cache flash device having an update address storage means provided with a plurality of areas each having one entry, the area being for storing data addresses. Monitor the above system bus Thus, data update in the cache memory is detected, and based on the update address at which the data has been updated and the identification number of the processor that has performed the data update, any one of the areas of the update address storage means is determined. Selecting an area and storing the update address in the selected area; and, by monitoring the system bus, detecting writing back of the data held by the dirty block to the main memory and detecting the writing. Based on the returned write-back address and the identification number of the processor that performed the write-back, any one of the areas of the update address storage means is selected and stored in the selected area. The update address is compared with the write-back address, and when they match, the update address stored in the selected area is compared. And a step of sequentially reading all update addresses stored in the update address storage means and preparing the read update addresses so that the processor can sequentially read the update addresses. Possible recording medium. 73. At least one processor provided with a copy-back type direct-mapped cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. A dirty block, which is used in a computer provided and is provided corresponding to each cache block secured in the cache memory and is a cache block in a state of holding data to be written back to the main memory, is held. A cache flash device is provided which has an area for storing data addresses, each area having one entry, and an update address storage means having a plurality of counters provided corresponding to this area. Program for recording A recording medium, detecting data update in the cache memory by monitoring the system bus, and based on an update address at which data is updated and an identification number of the processor that has performed data update, Selecting one of the areas in the update address storage means, storing the update address in the selected area, incrementing the counter corresponding to the area, and monitoring the system bus Thus, writing back of the data held by the dirty block to the main memory is detected, and the update address storage is performed based on the write back address at which the write back was performed and the identification number of the processor that performed the write back. Select one of the areas of the means, and select the area corresponding to the selected area. Decrementing a counter, and sequentially reading update addresses stored in an area where the value of a counter corresponding to the area is not an initial value among the areas provided in the update address storage means, and reading the read update address into the processor. And a computer-readable recording medium on which a program for executing a procedure for preparing to be sequentially read is recorded. 74. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. An area for storing an address of data held by a dirty block, which is used in a computer and is a cache block in a state of holding data to be written back to the main memory among cache blocks secured in the cache memory. A storage medium storing a program for controlling a cache flash device having an update address storage means provided with a plurality of data storage means, wherein a data update in the cache memory is detected by monitoring the system bus, and the data update is performed. There was an update address and A step of selecting any one of the areas of the update address storage means based on the identification number of the processor that has performed the data update, and storing the update address in the selected area; Comparing the number of empty entries in the area selected at the time of data update with a predetermined value, and when the number of empty entries falls below the predetermined value, selects one of the update addresses already stored in the area; A command for requesting the main memory to write back the data held by the dirty block indicated by the selected update address to the main memory is issued to the system bus, and the entry storing the update address is set as an empty entry. Procedure, and in response to an instruction from the processor, updates all update addresses stored in the update address storage means. Computer-readable recording a program for executing a sequential reading and a command for requesting the system memory to write back the data held by the dirty block indicated by the read updated address to the main memory, to the system bus. recoding media. 75. At least one processor having a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. An area for storing an address of data held by a dirty block, which is a cache block used to hold data to be written back to the main memory among cache blocks secured in the cache memory and used in the computer. A storage medium storing a program for controlling a cache flash device having an update address storage means provided with a plurality of data storage means, wherein a data update on the cache memory is detected by monitoring the system bus, and the data update is performed. There was an update address and A step of selecting one of the areas of the update address storage means based on the identification number of the processor that has performed the data update and storing the update address in the selected area; By monitoring the system bus, the write-back of the data held by the dirty block to the main memory is detected, and based on the write-back address where the write-back was performed and the identification number of the processor that performed the write-back, Any one of the areas in the update address storage means is selected, and a search is performed for a predetermined time to determine whether or not the selected area has an update address that matches the write-back address. If an update address that matches the address is detected, the procedure for deleting the update address and the free space in the area selected at the time of data update are performed. The number of birds is compared with a predetermined value, and when the number of empty entries is smaller than the predetermined value, one of the update addresses already stored in the area is selected and indicated by the selected update address. Issuing a command requesting writing back of the data held by the dirty block to the main memory to the system bus, and setting the entry storing the updated address as a free entry, and an instruction from the processor. In response to the command, all the update addresses stored in the update address storage means are sequentially read, and a command requesting the data stored in the dirty block indicated by the read update address to be written back to the main memory is issued. Computer recording a program for executing the above-mentioned procedure for issuing to the system bus A readable recording medium. 76. At least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory, and a system bus connecting the at least one processor and the main memory. An area for storing an address of data held by a dirty block, which is used in a computer and is a cache block in a state of holding data to be written back to the main memory among cache blocks secured in the cache memory. A storage medium storing a program for controlling a cache flash device having an update address storage means provided with a plurality of data storage means, wherein a data update in the cache memory is detected by monitoring the system bus, and the data update is performed. There was an update address and A step of selecting any one of the areas of the update address storage means based on the identification number of the processor that has performed the data update, and storing the update address in the selected area; By monitoring the system bus, the write-back of the data held by the dirty block to the main memory is detected, and based on the write-back address where the write-back was performed and the identification number of the processor that performed the write-back, Any one of the areas of the update address storage means is selected, and the cache flash device should next process whether or not there is an update address that matches the write-back address in the selected area. Search until a command is detected.If an update address that matches the write-back address is detected, the update address is deleted. And comparing the number of empty entries in the area selected at the time of updating the data with a predetermined value, and when the number of empty entries falls below the predetermined value, any one of the update addresses already stored in the area. One is selected, a command is issued to the system bus requesting that the data held by the dirty block indicated by the selected update address be written back to the main memory, and the update address is stored. In response to an instruction from the processor, a procedure for setting an entry to an empty entry, and sequentially reading all update addresses stored in the update address storage means, and holding the dirty block indicated by the read update address Issue a command to the system bus to request that data be written back to the main memory. And a computer-readable recording medium recording a program for executing the steps.