JPS5853075A - Information processor provided with high speed separation buffer - Google Patents

Abstract

PURPOSE:To speed up an access and to improve the processing performance, by separating an address conversion table into two, for instruction used and operand use and independently operating them for an instruction buffer use and an operand buffer use. CONSTITUTION:An instruction buffer system consists of an instruction address conversion table 1, an instruction buffer 2 and an instruction buffer controller 3 controlling the both, and an operand buffer system is made up of an operand address conversion table 4, an operand buffer system 5, and an operand buffer controller 6 controlling the both. The two systems can independently be operated. Thus, high speed accessing can be done to increase the processing performance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device equipped with a separate buffer for high-speed access.

Conventionally, this type of information processing apparatus is provided with separate buffers for instructions and operands, but an address conversion table is commonly used for instructions and operands. To do so, access the address translation table.

It was not possible to do this for instructions and operands at the same time. Therefore, 1 For example, Japanese Patent Application No. 1977-1.7
No. 6974, ``Address Buffer Memory System,'' unless we find a way to effectively apply the high-speed, high-capacity buffer technology described in ``Address Buffer Memory System.'' By adopting only one or the other, one had to be prepared for a drop in processing performance. or,
In order to avoid the need for address translation for instructions and operands to conflict with each other, resulting in performance degradation, a shared address translation table is used to translate addresses for two branch destinations in the case of one branch instruction. There have been various drawbacks in that the instruction buffer can only be accessed after accessing the instruction buffer, which slows down the readout time of the nine branch destination instructions and degrades processing performance for branch instructions.

An object of the present invention is to eliminate the above-mentioned drawbacks of the conventional art by providing two sets of address translation tables, one for instructions and one for operands, and using each address translation table as a bare one for each of the instruction buffer and operand buffer. An object of the present invention is to provide an information processing device equipped with a high-speed separate buffer that can perform and the means to do so.

Part of the information stored in the memory is kept as a copy for instructions and operands separately.9277
an instruction register; at least one address generation means for generating a logical address according to the contents specified by the instruction register; and an instruction address conversion unit for converting the logical address into a physical address. comprising a table, an instruction buffer accessed by a logical address or a physical address, an operand address conversion table for converting a logical address to a physical address, and an operand buffer accessed by a logical address or a physical address, The output of the at least one address generation means is given as an address to at least one of the instruction address translation table and the instruction buffer, and the operand address translation table and the operand buffer, and includes address translation. An information processing device equipped with a high-speed separate buffer characterized in that memory access is performed independently for instructions and operands is obtained.

Next, an information processing apparatus according to the present invention will be described in detail with reference to two embodiments and the drawings.

FIG. 1 shows a block diagram of an embodiment according to the present invention. In this figure, an instruction buffer system is constituted by an instruction address conversion table 1, an instruction buffer 2, and an instruction buffer controller 3 that controls both of them.

An operand buffer system is composed of an operand address conversion table 4, an operand buffer 5, and an operand buffer controller 6 that controls both of them. ii = The instruction and operand hardware systems can operate independently.

Although the purposes of use are different, their functions are the same.

Further, it can be concretely constructed by various modifications of buffer systems including conventionally known address conversion tables. for example.

Address conversion table 1.4 is a conversion table memory,
The buffer 2.5 includes a buffer memory, a management table for the buffer memory, a comparator, and a selection circuit. or.

The addresses used to access buffers 2 and 5 may be logical or physical addresses, but in this embodiment, 4! In order to achieve this effect, a configuration such as that described in the above-mentioned Japanese Patent Application No. 176974/1980 is applied, and access can be made using a logical address.

The instruction register 7 holds the instruction read out from the instruction buffer 2, specifies the control operation to be executed, and specifies, to the address generation circuit 8, a method of generating a logical address, which is an access address to the memory. The address generation circuit 8 is a penis register as is known from the prior art.

It is composed of an index register, an adder circuit, etc., and generates a logical address that is a sum of the pace, index, and f-placement, and sends it to the instruction address register 9. Alternatively, it is given to the operand address register 11. The operand address renostar 11 receives a logical address other than the branch destination address indicated by the branch instruction generated by the address generation circuit 8 as the address of the memory operand used by the instruction, and provides it to the operand buffer system. The land can be read from the address or given as a write address.

Instruction address register 9 indicates that 1 branch instruction is assigned to instruction register 7.
The logical address generated by the address generation circuit 8 as the branch destination address is always received as a predicted preemption υ when the branch is successful, or it is incremented by the address update circuit 10. Receive instruction address. It then holds the address of the instruction to be executed or scheduled to be executed first, and provides this address to the instruction buffer system to read the instruction. The address update circuit 10 is.

To execute instructions lined up at consecutive addresses, except when a branch occurs due to a branch instruction.

It operates to add the length of the instruction to the address indicated by the instruction address register 9 and return the result to the instruction address register 9.

Receives the operand read from the operand and performs the control operation specified by the instruction with the internally held arithmetic register.Then, if storage into memory is required, creates the data to be written and reads the operand. data to the buffer 6 for writing. The memory access controller 13 includes an instruction buffer controller 3. Alternatively, the operand buffer controller 6 determines whether the data to be accessed is not held in the buffer 2.5 or when it is necessary to store the data in the memory. work to control the situation.

As is clear from the above explanation, according to the present invention, one address translation table is separated into one for instructions and one for operands, and by linking them with buffers for instructions and operands and operating them independently, a large-capacity The panzer memory for instructions and operands can be accessed in parallel and at high speed, which has a significant effect on improving processing performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In the figure, 1 address conversion table for service instructions,
2 is an instruction buffer, 3 is an instruction buffer controller, 4 is an operand address conversion table, 5 is an operand buffer, 6 is an operand buffer controller, 7 is an instruction register, 8 is an address generation circuit, and 9 is an instruction Address register. 10 is an address update circuit, 11 is an operand address register, 12 is an arithmetic controller, and 13 is a memory access controller.

Claims (1)

[Scope of Claims] 1. A means for recognizing a logical address implying an access position to the memory and converting it into a physical address specifying the access position; In an information processing apparatus configured to include means for separately holding information for use and for operand. An instruction register, at least one address generation means for generating a logical address according to contents specified by the instruction register, and an instruction address conversion table for converting a logical address into a physical address. It includes an instruction buffer that is accessed using a logical address or a physical address, an operand address conversion table that converts a logical address into a physical address, and an operand buffer that is accessed using a logical address or a physical address. The output of at least one of the address generating means is. An address is given to at least one of the instruction address translation table and the instruction buffer, and the operand address translation table and the operand buffer, and memory access including address translation is performed for instructions and operands. What is claimed is: 1. An information processing device equipped with a high-speed separation buffer, characterized in that the processing is performed independently.