JPS6134628A - Computer provided with tag - Google Patents

Abstract

PURPOSE:To generate a format of a data indicated by a pointer, from a value of the pointer by assigning a storage area of information being on a main storage device, in accordance with a format of information classified by a tag. CONSTITUTION:In case of a main storage access, a tag generating mechanism 16 is started, when a control latch 41 is set by a starting line 40 from a control part 13 of a processor 3. A selector 42 inputs a storage address of an address line 22 to a tag memory 43. As for the tag memory 43, for instance, a data area is assigned by a block unit of 64 kilobytes. If a storage address length is set as 32 bits, this block address is determined by the upper 16 bits of a pointer. Accordingly, this computer is constituted so as to store a tag table to be indexed by this 16 bits, and by the upper 16 bits of an input storage address of a signal line 44, a tag of information assigned to this address which follows an area assignment is outputted to a signal line 45.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an improvement in a tagged computer configured to process tagged pointers and data.

As a computer system for processing data with a complex structure, there is a system in which data is designated by a pointer word in a tag section 1, and a tag is inserted into the data to control the data. Like this
In a computer, the information 86 is configured as, for example, as shown in FIG. 2, consisting of a tag section 1 that holds a tag, and a data/pointer section 2 that holds a pointer consisting of the data itself or address information of an information word. .

In the information word that holds a pointer (hereinafter referred to as a pointer edict), the address information of the data/pointer section 2 is the address information of the information word that holds data (hereinafter referred to as a data word) or the stored pointer word. The tag in the tag part 1 indicates the data of the information word pointed to by the pointer/the type of information in the pointer part 2, that is, whether it is a pointer, or if it is data, it is a numerical value, Data types such as characters are displayed.

In the case of a data word, the tag also indicates its data type.

As a result, before reading data from main memory etc.
Since the type can be known, the corresponding processing can be speeded up, and by using a control method that determines the processing according to the type depending on the data to be processed, programming of complex processing is made easier. There are other effects.

However, since normal computer systems do not use a structure that attaches tags to data, special considerations must be taken when using the components of a normal computer system for a tagged computer as described above. may be required.

[Prior Art and Problems to be Solved by the Invention] FIG. 3 shows an example of the structure of a main body of a tagged computer, which is composed of a processing device 3 having a function of processing tagged information words and a main storage device 4.

The main storage device 4 stores both the above-mentioned information words, that is, data words and pointer words, and is configured so that, in processing, both of them are, in principle, pointed to by the pointer of the pointer word.

In general, computers are often configured with a bit length of about 8 bits as the minimum unit (hide), and an integer power multiple of 2, especially 4 times (4hide), as the basic unit of data to express numerical values, etc. The main memory 4 is configured accordingly, e.g.
Alternatively, it is configured with 8 hides as an access unit.

Conventionally, in a computer with such a configuration, when using the pointer word and data word, the tag part l can be at most 8 bits, so one hide in one word is used as tag part 1, and the remaining three hides are used as data. /It was applied to pointer part 2.

However, for numerical data, etc., a minimum bit length of approximately 4 bytes is required in practice, as is employed in many conventional methods.

In addition, as the memory address space is expanding in recent years due to faster processing and easier programming, it is necessary to express the address using a bit length that is at least equivalent to the basic unit of numerical data. It is hoped that it can be used.

If these requirements were to be met, the pointer word would have a 5-hide structure, but if a word with such a structure were to be stored in the main memory 4 with the above structure, access and processing would become complicated. There is a problem that processing efficiency is reduced.

[Means for solving problems]

The above problem arises when processing a word that is composed of a data/pointer section that holds data or a pointer, and a tag section that holds a tag that displays the type of data or the type of data pointed to by the pointer. buffer to hold,
a main storage device that stores information in the pointer/data section;
and means for generating a tag based on the address value of the main memory, and means for generating the information read from the main memory as data/data.
This problem can be solved by the tagging computer of the present invention, which has means for storing in the buffer so as to form a word having a pointer part and a tag generated by the tag generating means as a tag part.

[Effect]

That is, by allocating the storage area of information on the main storage device 4 according to the type of information classified by tag, for example,
Enables generation of the data type pointed to by a pointer value.

In this way, the information stored in the main storage device 4 is only the data/pointer part 2 excluding the tag part 1 of the information word.
In the process of reading the information word (data/pointer section) from the main storage device 4 to the buffer of the processing device 3, a tag is generated from the storage address of the data/pointer section and added to the data/pointer section, and the tag is added to the buffer. Store in.

Therefore, each data/pointer section on the main memory device 4 can use the entirety of one memory word of, for example, 4 bytes, and in the processing device 3, it becomes a tagged information word of, for example, 5 bytes, and is used in the tagged computer system. It can be processed.

Therefore, there is no need to make the storage device 4 have a special configuration, and there is no need to complicate address control etc. in the processing device 3.
It becomes possible to configure a desirable tagged computer.

〔Example〕

FIG. 1(a) is a block diagram showing one embodiment of the present invention.

In the figure, a buffer 10 is a relatively small-capacity, high-speed storage device that forms part of the configuration of the processing device 3. Logically, it is used to store pointer words and data words stored in the main storage device 4. It retains copies of some words.

The buffer 10 has a main area 11 for storing a data/pointer section consisting of, for example, 4 bytes, and a tag area 12 consisting of a storage area of, for example, 1 hide corresponding to each main area 11. The structure is such that five hides, which are connected areas, are accessed as one information word.

The numbers in parentheses attached to lines connecting blocks in the figure indicate an example of the byte width of the information unit transferred by the line.

When a storage address to which access is requested is specified by the control unit 13 of the processing word W3 via the signal line 14, the buffer 10 is first searched for the data or pointer word at the corresponding storage address, as is well known. In this case, the buffer 10 is updated using data read out from the buffer 10 to the control unit 13 or transferred from the control unit 13.

If the data or pointer word at the requested storage address is not in the buffer 10, the data or pointer word is read from the main storage device 4 according to the storage address set in the address register 15 and stored in the buffer 10 for use. . At this time, there are controls such as replacement of the contents of the buffer 10, but since they may be performed using known buffer control techniques, their explanation will be omitted.

In this embodiment, the storage area of the main storage device 4 is, for example, a numerical data area 30, as shown in the explanatory diagram of FIG.
, a pointer area 31, a character data area 32, and a vector data area 33, areas are allocated to each type of information classified by tags in units of blocks each consisting of consecutive storage addresses.

Furthermore, among the information words, only the data/pointer section 2 shown in FIG. 2 is stored in the main storage device 4, and the tag section 1 is not actually stored.

When accessing main memory 4, address register 1
The memory address of 5 is the main rudder 4. # When the data or pointer (data/pointer part) of the corresponding storage area is read out after being transferred to the device 4, it is transferred to the buffer 10 via the signal line 2° and is also input to the tag generation mechanism 16. The storage address of the access request is also input to the tag generation mechanism 16 via the address line 22 from the address register 5.

FIG. 1(c) is a block diagram showing the detailed configuration of the tag generation mechanism 16.

In accessing the main memory, the tag generation mechanism 16 uses the control latch 41 by the activation line 4o from the control unit 13 of the processing device 3.
is set and starts. The selector 42 is controlled by the signal from the control launch 40 to input the storage address on the address line 22 to the tag memory 43.

The tag memory 43 stores, for example, data MJj! If i is allocated in blocks of 64 kilobytes and the storage address length is 32 bits, the block address is determined by the upper 16 bits of the pointer (storage address), so the tag table to be indexed using these 16 bits is stored. By using the upper 16 bits of the long sword memory address on the signal line 44, the tag of information assigned to the address according to the area allocation shown in FIG. 1 (bl) is output to the signal line 45.

If the storage address passed from the address line 22 to the signal line 44 is not in the pointer area 31, the output of the signal line 45 is transferred to the buffer 10 via the signal line 21 as the target tag.

If this storage address is in the pointer area 31,
The tag value on the signal line 45 is detected by the pointer type detection circuit 46, and the tag transfer to the buffer 10 is blocked by the signal on the output signal line 47 at the gate 48, and the control latch old is reset.

As a result, the selector 42 receives the signal line 2 from the main memory 4.
Pass read data of 0 to signal line 44.

At this time, the storage address on the signal line 22 is a pointer area, and therefore the storage address, which is a pointer in the pointer word, is read out from the main memory 4 on the signal line 20.

Therefore, with this storage address, the tag memory 43 operates in the same manner as described above and outputs the tag value to the signal line 45.

This tag value is transferred to the buffer 10 via the signal line 21. Note that the tag value in this case may be a pointer tag again, but this time the control latch 41 has been reset, so the pointer type detection circuit 46 does not operate (by control of the signal line 48). The tag indicating the pointer is directly transferred to the buffer 10 via the signal line 21.

In the buffer 10, the data or pointer from the signal line 20 is stored in the main area 11, and the contents of the signal line 21 are stored in the tag area 1.
Store it in the corresponding area of 2.

In addition, in the case where the data is a numerical value, in the case where the data itself is exceptionally placed in the pointer part of the pointer word, for example, in the tag generation mechanism 16, the tag generated from the storage address of the address line 22 is a numerical value. If it is data, the main memory W4 is accessed to read the corresponding data, and the data and the previously generated tag are stored in the buffer 10.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a tagged computer having a pointer and data having a required hint length can be configured without reducing processing efficiency or using a specially configured storage device. Because you can
There is a significant industrial effect in that the performance of the tagged computer can be improved -1- and the range of application can be expanded.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a tagged pointer, and FIG. 3 is a configuration diagram of a computer. In the figure, ■ is a tag section, 2 is a data/pointer section, 3 is a processing unit, 4 is a main memory, 10 is a buffer, 15 is an address register, 16 is a tag generation mechanism,
41 is a control launch, 42 is a selector, 43
Reference numeral 46 indicates a tag memory, and 46 indicates a pointer type detection circuit. Agent Patent Attorney Weighing Koshibe Houki 1 Ward (ku) Kaya 1 En<S

Claims (1)

[Claims] In processing a word consisting of a data/pointer section holding data or a pointer and a tag section holding a tag indicating the type of the data or the type of data pointed to by the pointer, the buffer holding the word; a main memory device for storing information of a pointer/data section, a means for generating a tag based on an address value of the main memory device, and information read from the main memory device as a data/pointer section;
A tagged computer characterized by comprising means for storing in the buffer a word having a tag part formed by the tag generated by the tag generating means.