JPS6385949A - Cache memory storing system - Google Patents

Abstract

PURPOSE:To improve the lowering of the performance of a store processing, by applying the store processing on a bypass buffer, when the coincidence of addresses is detected by a detection circuit which detects the coincidence of a store address and a bypass buffer address. CONSTITUTION:A request register 1 is a register consisting of a request code part and an address part to hold a bit of address information. The bit of address information is inputted to a store address buffer 4, and a bypass buffer address register 5, and an address at time of storing, and the address of a bypass buffer 6 are held respectively. At the time of writing the content of a store data buffer 7 on a data array 9, the content of the store address buffer 4 corresponding to the content of the store data buffer 7, is compared with that of the bypass buffer address register 5 at a comparator 12, and when the coincidence is obtained, a result is informed to a bypass buffer control circuit 13. And an instruction to write the data from the store data buffer 7 to the data array 9, and the instruction to write the data to an area corresponding to the bypass buffer 6, are issued.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a cache memory control device.

In particular, it relates to a store method when writing data from store buffer 1 to cache memory.

[Conventional technology]

Conventionally, in a cache memory control device having this type of store buffer, when writing data from the store buffer to the cache memory.

Waiting until the read process (hereinafter referred to as block load; a block is a unit of copying of the cache memory and main memory, and is assumed to be 64 bytes here) of the data output to the main memory before this write is completed, After the block load data is written to the cache memory, the above write process (store process) is performed.

In other words, the store process is performed after the block load data has been written to the cache memory in order to prevent the block load data from being rewritten correctly by performing the store process first.

[Problem that the invention seeks to solve]

By the way, in the case of the conventional store method mentioned above.

While a block load is being performed to main memory,
Writing from the store buffer to cache memory is always inhibited. Therefore, the empty time of cache memory (during block loading).

Since subsequent read accesses are made to wait, the cache memory (not used) cannot be used for store processing, and as a result, a situation may arise in which subsequent read accesses must be stopped and cache memory is used. As a result, there is a problem that system performance deteriorates.

[Means for solving the problem] The present invention includes a bypass buffer that temporarily holds data read from the main memory, and a bypass buffer 1 that holds the main memory address of the data held in the bypass buffer. an address register; an address match detection circuit that detects a match between the read address of the bypass buffer 1 address register and the read address of the store address buffer 1; and an address match detection circuit that detects a match between the read address of the bypass buffer 1 address register and the read address of the store address buffer 1; and a control means for rewriting the corresponding area of the bypass buffer.

〔Example〕

The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention. Referring to FIG. 1, a request register 1 is a register that holds address information consisting of a request code section including the type of access request and instruction contents, and an address section of the access request.

The request code portion is input to the main memory access control circuit 2 via a connection 50, while the address portion is stored in the address array 14. The main memory access control circuit 2 decodes this request code section and is controlled by the address section from the address array 14, and generates and distributes necessary control signals to each section. Furthermore, the address information is input to the switching circuit 6 through a connection 51, and becomes a main memory request address as described later. Additionally, address information is input to the store address buffer 14 and bypass buffer address register 5 through connections 56 and 54, respectively.
Address and Piverse Buffer 6 at the time of storage
retains the address of

Store data at the time of a store request is input to the store data buffer 7 through a connection 55.

The data is input from a connection 56 to the main memory, from a connection 57 through the switching circuit 8 to the data array 9, and from a connection 58 through the switching circuit 10 to the bypass buffer 6.

The main memory read data is stored from the connection 59 through the entire switching circuit 10 to the bypass buffer y6Vr-n.

On the other hand, data is returned to the request source through the switching circuit 11 from the connection 60 or 61.

When writing the contents (data) of store data buffer 7 to data array 9, the contents (address) of store address buffer 14 corresponding to the contents of store buffer 1 data 7 are read out and sent to comparison circuit 12 via connection 62. . on the other hand.

The contents of the bypass buffer address register 5, which stores the address of the data held in the bypass buffer 6, are sent to the comparison circuit 12.

A comparison circuit 12 compares the contents of the store address buffer 14 and the contents of the bypass buffer 1 address register 5.

When the contents of the store address buffer 4 and the contents of the bypass buffer 1 address register 5 match, that is, when the block addresses match, the bypass buffer control circuit 13 is notified of the match result. At the same time as data is written from the store data buffer 7 to the data array 9, the connection 58 instructs the writing to the corresponding area of the bypass buffer 16 via the switching circuit 10.

In the above-described embodiment, when the comparison circuit 12 detects a match of addresses, writing from the store data buffer 7 to the data array 9 is continued without being inhibited.
This is because the corresponding data exists only in bypass buffer B, so there is no problem even if writing is inhibited.

〔Effect of the invention〕

As explained above, the present invention includes a detection circuit that detects a match between a store address and a bypass buffer address, and when the detection circuit detects an address match, stores processing is performed on the bypass buffer. Since this is done, the performance deterioration of store processing can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1.5...Register, 2.13...Control circuit, 3
,8゜10.11.12...Switching circuit, 4...Store buffer 6...Bypass buffer, 7...Store data buffer, 9...Data array, 14...Address array.

Claims (1)

[Claims] 1. An address array that stores a copy of the address of the main memory, a data array that stores a copy of the data of the main memory, and a store address that temporarily stores a store address that includes the address to be updated in the address array. A cache memory control device having a buffer and a store data buffer that temporarily stores store data that is update data of the data array, a bypass buffer that temporarily stores data read from the main storage device; a bypass buffer address register that holds a main memory address of data held in a bypass buffer; an address match detection circuit that detects a match between a read address of the bypass buffer address register and a read address of the store address buffer;
A cache memory store system comprising: control means for rewriting a corresponding area of the bypass buffer with data of the store data buffer based on the output of the address match detection circuit.