JPS6385948A - Cache memory storing system - Google Patents

Abstract

PURPOSE:To prevent the performance of a store processing from being lowered, by writing the content of a bypass buffer on a data array taking precedence over the store processing, when the coincidence of addresses is detected by a detection circuit which detects the coincidence of a store address and a bypass buffer address. CONSTITUTION:A request register 1 is a register to hold a bit of address information. The bit of address information is inputted to a store address buffer 4, and a bypass buffer address register 5, and an address at time of storing, and the address of a bypass buffer 6, are held respectively. At the time of writing the content of a store data buffer 7 on the data array 9, the content of the store address buffer 4 is compared with that of the bypass buffer address register 5 at a comparator 12, and when the coincidence is obtained, a result is informed to a bypass buffer control circuit 13. After the suppression of write on the data array 9 is instructed, and an instruction to write the content of the bypass buffer 6 preferably is issued, and the write is completed, the suppression of the write on the data array 9 from the store data buffer is canceled, and the store processing is continued.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a cache memory control device.

In particular, it relates to a store method when writing data from a store buffer to a cache memory.

[Conventional technology]

Conventionally, in a cache memory control device having this type of store buffer, when data is written from the store buffer to the cache memory, a read process (hereinafter referred to as a block load; hereinafter referred to as a block load) of the data issued to the main storage device before the write is performed. A block is a unit of copies of cache memory and main memory, and is assumed to be 64 bytes here). After the block load data is written to the cache memory, the above write process (store process) is performed. has been done. In other words.

In order to prevent the block load data from being rewritten incorrectly due to the preceding store process, the store process is performed after the block load data is written to the cache memory.

[Problem that the invention seeks to solve]

By the way, in the case of the conventional store method mentioned above.

While a block is being loaded to the main memory, writing from the store buffer to the cache memory is always inhibited. Therefore, the empty time of the cache memory (during block loading, the cache memory is not used because subsequent read accesses are made to wait) cannot be used for store processing.

Therefore, subsequent read access is stopped and cache memo I
J' is often required to be used, and as a result, there is a problem in that system performance deteriorates.

[Means for Solving the Problems] In the present invention, the data e read from the main memory device is provided with a bypass buffer for temporarily holding the data e- and the Pino J? An address match detection circuit that detects a match between the main memory address of the data held in the spather and the read address of the IP spaffer address register and the read address of the &E store address puffer. and a control means for giving priority to writing from the pin data array to the data array based on the output of the address matching circuit.

〔Example〕

The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention. Referring to FIG. 1, a request register 1 is a register that holds address information consisting of a request code section including the type of access request and instruction contents, and an address section of the access request.

The request code section is input to the main memory access control circuit 2 through a connection 50, while the address section is controlled by the address section from the address array 14 to generate and distribute necessary control signals to each section. Furthermore, the address information is input to the switching circuit 3 through a connection 51, and becomes a main memory request address as described later. Furthermore, address information is input to the store address buffer 4 and pi A' spaffer address register 5 via connections 53 and 54, respectively.

The store address buffer 4 and the bypass buffer address register 5 hold the address at the time of storage and the address of the bypass buffer 6, respectively.

Store data at the time of a store request is input to the store data buffer 7 via a connection 55, to the main memory via a connection 56, to the data array 9 via a connection 57 through a switching circuit 8, and from connection 58 to the bypass buffer 6 via a switching circuit 10. be done.

Main memory read data is stored in bypass buffer 6 via connection 59 and switching circuit 10, while data is returned to the request source via connection 60 or 61 via switching circuit 11.

When writing the contents (data) of store data buffer 7 to data array 9, the contents (address) of store address buffer 4 corresponding to the contents of store buffer data 7 are read and sent to comparator circuit 12 via connection 62. On the other hand, the address of the data held in the buffer 6 is stored. The contents of the buffer address register 5 are sent to the comparison circuit 12, and the contents of the store address buffer 4 are compared with the contents of the bypass address register 5.

If the contents of the store address buffer 4 match i<' the contents of the buffer address register 5.

That is, if the block addresses match, the pinox buffer control circuit 13 is notified of this matching result. The PINO 4 spaffer control circuit 13 instructs to inhibit writing from the store data buffer 7 to the data array 9, and sends a PINO J? It instructs that the contents of the spaffer 6 be preferentially written to the data array 9 through the switching circuit 8 via the connection 63. When this writing is completed, the write inhibition from the store data buffer 7 to the data array 9 is released and the store processing is continued.

〔Effect of the invention〕

As explained above, the present invention includes a detection circuit that detects a match between a store address and a bypass buffer address, and when an address match is detected by the detection circuit, the contents of the bypass buffer are processed with priority over store processing. Writing to the data array has the effect of improving performance degradation in store processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1.5...Register, 2.13...Control circuit.

Claims (1)

[Claims] 1. An address array that stores a copy of the address of the main memory, a data array that stores a copy of the data of the main memory, and a store address that temporarily stores a store address that includes the address to be updated in the address array. A cache memory control device having a buffer and a store data buffer that temporarily stores store data that is update data of the data array, a bypass buffer that temporarily stores data read from the main storage device; a bypass buffer address register that holds a main memory address of data held in a bypass buffer; an address match detection circuit that detects a match between a read address of the bypass buffer address register and a read address of the store address buffer;
A cache memory store system comprising: control means for giving priority to writing from the bypass buffer to the data array based on the output of the address match detection circuit.