KR860002122B1 - Laser beam printer - Google Patents

Abstract

A video signal generator for a page buffer of the laser printer does not use a direct access memory(DMA) which switches the data bus of the page buffer memory(50 to the video logic (40) after the data bus is used by a CPU (10). The data and address buses of the page buffer memory are used exclusively in the CPU and the video logic. A logic gate(100) for controlling the transfer of the bus with a control signal(SEL) comprises a bus transceiver, a bus driver, and a data selector.

Description

Video signal generator for page buffer of laser beam printer and its operation method

1 is a block diagram of a conventional page buffer memory.

2 is a block diagram of the present invention.

3 is a data flow diagram in the page buffer memory of the present invention.

4 is a detailed circuit diagram of the operation of the page buffer memory of the present invention.

* Explanation of symbols for main parts of the drawings

10: Central processing unit (CPU) 20: Input, output device (I / O port)

30: system memory 40: video logic

50: Memory for page buffer 70, 80: Bus Transciver

90: data selector 100: logic gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for generating a video signal in a laser beam printer, and more particularly, to supply data to a video logic circuit by performing a task of stacking data received from a computer in a memory. It is about how to operate.

As a conventional apparatus and its operation method, as shown in FIG. 1, a central processing unit (CPU) 10, an input / output (I / O) apparatus 20, a system memory 30, and video logic (Video) are shown. Logic) 40, a page buffer memory 50, and a Direct Memory Assess (hereinafter abbreviated as " DMA ") 60 for performing a disease mission of a data bus therebetween. As it is, the operation state is described as follows.

First, the CPU 10 receives data from a computer through an input and output device 20, and then stacks the data in a page buffer memo 40 after processing the data.

The data is then taken and used in the instant of the video logic 40. In this case, the data bus connects the data bus from the central processing unit 10 to the video logic 40. 60). That is, the DMA 60 holds the central processing unit 10 in a holding state so that the data bus output from the central processing unit 10 is in a high impedance state so that the video logic 40 buffers the page. It becomes the state which the memory 50 can use.

As such, the conventional device is not only very expensive due to the use of the expensive DMA 40, but also the DMA 60 is the central processing unit while the video logic 50 is operated to use the page buffer memory 50. Since holding the 10, the central processing unit 10 has a problem that can not perform other tasks.

In view of the above-described problems, the present invention causes the data processing unit of the page buffer memory 50 to move to the video logic 40 side after the CPU 10 uses the data bus of the page buffer memory 50. Inexpensive logic gate circuit is used instead of expensive DMA 60 to reduce the cost of the product, and the central processing unit 10 can be used even when the video logic 40 uses the page buffer memory 50. Is a window created so that it can continue to perform other tasks without entering the holding state, which will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, the present invention relates to a laser beam printer, comprising a central processing unit 10, an input and output device 20, a system memory 30, a video logic 40, and a faber. It consists of a logic gate 100 that controls the data bus and address bus of the buffer memory 50. The logic gate 100 is a bus transceiver 70, 80 as shown in FIG. And a data selector 90.

In the description of the drawings, reference numeral OE is an output enable terminal. When its signal is low, it is connected to the video logic 40, and when it is high, it is a terminal for outputting a signal that is open, and SEL is a control signal input terminal. to be.

Referring to the effects of the present invention configured as described above are as follows.

3 is a data flow diagram of a page buffer memory of the present invention;

A shows a process of receiving data of one page from the central processing unit 10 through the input / output device 20 from a computer (not shown) and stacking the data in the page buffer memory 50.

B is the page buffer memory 50 divided into one line of data unit, that is, the address where the first letter information of the line is set is determined and one line of character information is accumulated. After that, the CPU 10 transfers the data of the page buffer memory 50 to the system memory 30 by one line and performs processing to be suitable for the video logic 40. Shown,

C shows the process of re-adding to the corresponding area of the page buffer memory 50 after the above processing. When the processes A, B, and C as described above are completed to the last line, the CPU 10 uses the page buffer memory 50 to end.

Here, the video logic 40 does not operate while the CPU 10 uses the page buffer memory 50, and data of the page buffer memory 50 is also separated from the video logic 40. It is.

On the other hand, when printing starts, the video logic 40 operates to generate a video signal, and at the same time, the data bus and the address bus of the page buffer memory 50 are separated from the central processing unit 10 and the video is separated. Connected to logic 40. This will be described in detail with reference to FIG. 4 as follows.

The data bus output from the page buffer memory 50 is connected to the system data bus through the bus transceiver 70 and to the video logic 40 through the bus transceiver 80. At this time, if any one is selected by the control signal appearing in the control signal terminal SEL of the logic gate 100, the other output is in the high impedance state, the connection to the bus is terminated, the page buffer memory 50 The address bus also has a disease between the CPU 10 and the video logic 40.

Therefore, the data selector 90 selectively connects the address buses from two places to the page buffer memory 50.

The present invention operating as described above uses the data bus and the address bus of the page buffer memory exclusively in the central processing unit and the video logic, thereby avoiding the use of expensive conventional DMA to control the bus, and instead, it is inexpensive. In addition to lowering production costs by using in-logic gates, while the video logic uses memory for page buffers, the CPU can perform other tasks even if the CPU does not use memory for page buffers. .

Claims (2)

In using the data bus and the address bus of the page buffer memory 50 exclusively in the central processing unit 10 and the video logic 40, the address bus uses the data selector 90 and the central processing unit 10. The logic bus 100 is configured to control the disease of the bus as a control signal SEL using the bus transceiver 70 and the video transceiver 40 as the bus transceiver 80. A video signal generator for a page buffer of a laser beam printer. The data to be printed from the computer is piled up in the page buffer memory 50 in a single line unit, and the system memory 30 is used in a line unit suitable for the video logic 40 after stacking all the pages. And process it, and fill it into the corresponding space of the page buffer memory (50) again.

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