JPS58221437A - Controlling device of picturing - Google Patents

Controlling device of picturing

Info

Publication number
JPS58221437A
JPS58221437A JP57102243A JP10224382A JPS58221437A JP S58221437 A JPS58221437 A JP S58221437A JP 57102243 A JP57102243 A JP 57102243A JP 10224382 A JP10224382 A JP 10224382A JP S58221437 A JPS58221437 A JP S58221437A
Authority
JP
Japan
Prior art keywords
memory
block
control computer
data
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57102243A
Other languages
Japanese (ja)
Inventor
Tadao Konishi
小西 忠雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57102243A priority Critical patent/JPS58221437A/en
Publication of JPS58221437A publication Critical patent/JPS58221437A/en
Pending legal-status Critical Current

Links

Landscapes

  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE:To transfer picturizing data at a high speed and to shorten the operation time of picturing, by dividing a picturized memory into several blocks and providing the titled device with a switching circuit to connect each block selectively and directly to a control computer. CONSTITUTION:The picturized memory 11 is divided into several blocks and one of them is selectively switched by a switching circuit 10 and connected to a main memory bus 8 of the control computer 1. Consequently, the selected block is enabled to execute the same transfer processing as that of a main memory 3. Therefore, the picturizing data can be transmitted from a file memory 2 to the picturized memory 11 only by one transfer and a large scale block determined by the block size of the memory 11 and the size of an address space to be assigned to the memory 11 can be transferred independently of the size of the memory 3. By changing a block to be selected appropriately, the address space of the control computer 1 can be expanded.

Description

【発明の詳細な説明】 本発明は描画制御装置に関するものである。[Detailed description of the invention] The present invention relates to a drawing control device.

従来、電子線等によシ描画を行う描画装置では多量の描
画データを高速にアクセスする必要のため、第1図に示
すように描画ブロックに応じた描画データを、大容量デ
ィスクなどのファイルメモリー2から大容量ICメモリ
等により構成される描画メモリ5へ、描画メモリインタ
フェース4全通し1移し、この後描画制御系6により描
画機構部7に対する制御データ(例えばプシンキング、
位置、ビーム形状等)に変換して描画動作を行っている
。ところが、このような構成において、制御計算機1か
らみれば、描画メモリ5Fiインタフエース4を介した
外部メモリとして見なされ、データ転送にあたっては、
ファイルメモリ2からメインメモリ3へ一度直接転送な
どの手法でデータを移した後、メインメモリ3からあら
ためて描画メモリ5へ移す処理が行なわれる。そのため
、実装されたメインメモリ3のうち転送用バッファとし
て使用可能なメモリサイズおよび高速転送の多重化等の
制約を受け、データの転送速度が低下し、データネック
による描画速度の減少が発生しやすい等の欠点がある。
Conventionally, in drawing devices that perform drawing using electron beams, etc., it is necessary to access a large amount of drawing data at high speed. 2 to the drawing memory 5 configured with a large-capacity IC memory, etc., and then the drawing control system 6 transfers control data (for example, pushing,
position, beam shape, etc.) and performs the drawing operation. However, in such a configuration, from the perspective of the control computer 1, the drawing memory 5 is regarded as an external memory via the Fi interface 4, and in data transfer,
After the data is once transferred from the file memory 2 to the main memory 3 by a method such as direct transfer, a process of transferring the data from the main memory 3 to the drawing memory 5 is performed. Therefore, due to restrictions such as the memory size that can be used as a transfer buffer in the implemented main memory 3 and the multiplexing of high-speed transfers, the data transfer speed decreases, and the drawing speed is likely to decrease due to data neck. There are drawbacks such as.

又、描画データに対し制御計算機1によって演算をほど
こす場合、描画メモリ5よシメインメモリ3へ移すなど
してメインメモリ上で演算を行うため処理時間が長くな
る上、演算内容が実装メモリサイズの大きさで制約され
るなどの欠点があった。
Furthermore, when the control computer 1 performs calculations on the drawing data, the processing time is longer because the calculations are performed on the main memory, such as by moving them from the drawing memory 5 to the main memory 3, and the contents of the calculations are limited to the installed memory size. There were drawbacks such as being limited by the size of the

本発明の目的は、描画データの高速な転送が可能となる
と共に、描画のための演算処理時間を縮少し得るように
した描画制御装置を提供することにある。
An object of the present invention is to provide a drawing control device that enables high-speed transfer of drawing data and reduces calculation processing time for drawing.

本発明は、描画メモリを幾つかにブロックに分け、各ブ
ロックを選択的に制御計算機に直接接続する切換回路を
設けたものである。
In the present invention, a drawing memory is divided into several blocks, and a switching circuit is provided for selectively connecting each block directly to a control computer.

以下、実施例を用いて本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail using Examples.

第1図は本発明の一実施例を示すブロック図であって、
第1図と同一部分は同一記号で表わしている。同図にお
いて、描画メモリ11はいくつかのブロックに分けられ
、そのブロックの一つは切換回路10によシ制御計算機
1のメインメモリバス8に選択的に切換接続できるよう
に構成されている。従って、選択されたブロックについ
ては、メインメモリ3と同様の転送処理が可能になる。
FIG. 1 is a block diagram showing an embodiment of the present invention,
The same parts as in FIG. 1 are represented by the same symbols. In the figure, the drawing memory 11 is divided into several blocks, and one of the blocks is configured so that it can be selectively connected to the main memory bus 8 of the control computer 1 by a switching circuit 10. Therefore, transfer processing similar to that of the main memory 3 is possible for the selected block.

この結果、描画データはファイルメモリ2から一回の転
送で描画メモリ11へ送る事ができる。又、実装メイン
メモリ3のサイズにかかわりなく、描画メモリ11のブ
ロックサイズと、描画メモリ11に割当て得るアドレス
空間の大きさできまる大ブロツク転送が可能となる。又
、計算機1による図形演算にあたっては、メインメモリ
3と同等であり、演算速度の向上が図れる。そして、選
択するブロックを適時切り換える事により、制御計算機
1のアドレス空間を拡大できる。計算機1に接続されな
い他のブロックは、切換回路12によシ描画制御系6に
接続され、描画機構部7への制御データが作成される。
As a result, the drawing data can be sent from the file memory 2 to the drawing memory 11 in one transfer. Furthermore, regardless of the size of the main memory 3 mounted, large block transfer is possible, which is determined by the block size of the drawing memory 11 and the size of the address space that can be allocated to the drawing memory 11. Furthermore, when performing graphic calculations by the computer 1, it is equivalent to the main memory 3, and the calculation speed can be improved. The address space of the control computer 1 can be expanded by switching the blocks to be selected in a timely manner. The other blocks that are not connected to the computer 1 are connected to the drawing control system 6 through the switching circuit 12, and control data for the drawing mechanism section 7 is created.

第3図に、切換回路10の詳細を示す。アドレスセレク
ト回路20により、メモリバス8の上位アドレス線によ
り、描画ブロックアクセス信号23を得る。また、別途
計算機より制御されるブロック切換レジスタ27の出力
から指定すべきブロックセレクト信号24を得る。これ
等の信号よりバス接続信号25を得て、バス開閉スイッ
チ22を制御し、描画メモリ11との接続を行う。
FIG. 3 shows details of the switching circuit 10. The address select circuit 20 obtains a drawing block access signal 23 from the upper address line of the memory bus 8 . Further, a block select signal 24 to be specified is obtained from the output of a block switching register 27 which is separately controlled by a computer. A bus connection signal 25 is obtained from these signals to control the bus open/close switch 22 and connect to the drawing memory 11.

以上の説明から明らかなように本発明によれば、描画デ
ンタの高速転送が可能となり、また演算速度の向上が図
れるなどの効果がある。
As is clear from the above description, according to the present invention, it is possible to transfer drawing data at high speed, and the calculation speed can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の構成を示すブロック図、第2図は本発明
の一実施例を示すブロック図、第3図は切換回路の一例
を示す回路図である。 1・・・制御計算機、2・・・ファイルメモリ、3・・
・メインメモリ、4・・・描画メモリインタフェース、
5゜11・・・描画メモリ、6・・・描画制御系、7・
・・描画機構部、10.12・・・切換回路。 茅l 固 $2 囚
FIG. 1 is a block diagram showing a conventional configuration, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing an example of a switching circuit. 1... Control computer, 2... File memory, 3...
・Main memory, 4...Drawing memory interface,
5゜11...Drawing memory, 6...Drawing control system, 7.
...Drawing mechanism section, 10.12...Switching circuit. Kaya hard $2 prisoner

Claims (1)

【特許請求の範囲】[Claims] 1、描画データを制御計算機の制御下で大容量ファイル
メモリから受取り一時記憶する描画メモリを有し、上記
描画データに対した描画を電子線等を用いて行う描画制
御装置において、上記描画メモリを所定サイズのブロッ
ク別に選択的に上記制御計算機に直接接続する切換回路
を設けたことを特徴とする描画制御装置。
1. In a drawing control device that has a drawing memory that receives and temporarily stores drawing data from a large-capacity file memory under the control of a control computer, and performs drawing on the drawing data using an electron beam or the like, the drawing memory is A drawing control device comprising a switching circuit that selectively connects each block of a predetermined size directly to the control computer.
JP57102243A 1982-06-16 1982-06-16 Controlling device of picturing Pending JPS58221437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57102243A JPS58221437A (en) 1982-06-16 1982-06-16 Controlling device of picturing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57102243A JPS58221437A (en) 1982-06-16 1982-06-16 Controlling device of picturing

Publications (1)

Publication Number Publication Date
JPS58221437A true JPS58221437A (en) 1983-12-23

Family

ID=14322173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57102243A Pending JPS58221437A (en) 1982-06-16 1982-06-16 Controlling device of picturing

Country Status (1)

Country Link
JP (1) JPS58221437A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254290A (en) * 1985-09-03 1987-03-09 日本電気株式会社 Color graphic display unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254290A (en) * 1985-09-03 1987-03-09 日本電気株式会社 Color graphic display unit

Similar Documents

Publication Publication Date Title
US4922416A (en) Interface device end message storing with register and interrupt service registers for directing segmented message transfer between intelligent switch and microcomputer
JPS58221437A (en) Controlling device of picturing
JPS6242306B2 (en)
KR900005303A (en) Data processing unit
US5796753A (en) High speed test pattern transfer apparatus for semiconductor test system
JPH03204753A (en) Dma controller
EP0090137A3 (en) Access control system for digital data storage device
US6385684B1 (en) Intelligent PC add-in board
KR860002122B1 (en) Laser beam printer
KR940009830B1 (en) Control logic device
JPS58181134A (en) Data transfer circuit
JPS6053901B2 (en) Inter-processor information transfer method
JP2001084173A (en) Memory device
JPS6019534B2 (en) Transfer control device
KR0135894Y1 (en) Fifo using feedback method
KR19980033805A (en) Data Bus Selection Control Circuit of Semiconductor Memory Device
JPS6160163A (en) Data transfer system
JPS62245464A (en) Dma controller for electronic computer system
JPS5622157A (en) Process system multiplexing system
JPS61153770A (en) Image processor
JP2000242523A (en) Microprocessor and debugging device
JPH0329021A (en) Printer server
JPS61267852A (en) Data bus conversion system
JPH06161945A (en) Memory data transfer device
JPH01120661A (en) Memory control circuit