JPH01120661A - Memory control circuit - Google Patents

Abstract

PURPOSE:To realize simultaneous reading and writing actions between different addresses of two memories by designating simultaneously the addresses different from each other by an addition value to be added to an adder at both memories via a buffer and the adder. CONSTITUTION:An adder 11 is put into an address bus 20 connected between two memories 1 and 2. At the same time, buffer 8-10 are put into control lines connected between both memories 1 and 2. The buffers 8-10 are individually controlled by a DMA controller 5. Then an prescribed addition value is given to the adder 11 so that the addresses different from each other by said addition value are designated at one time at both memories 1 and 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for memory transfer in an information processing device or a communication device.

The present invention relates to a data communication device that requires a high real-time processing function, a large-volume high-speed data processing device that requires separation processing technology using multiple CPUs, a speed conversion buffer circuit for a digital multiplex and distributed communication device with different data transmission speeds, Applied to general-purpose packet switching equipment, etc.

〔overview〕

A memory control circuit comprising a control means for controlling data transfer between two memories, and in which a data bus, an address bus, and a control line are connected between the control means and the two memories; By providing an inserted adder and a buffer inserted into each of the above control lines, it is possible to simultaneously perform read and write addressing between different addresses in two memories. .

[Conventional technology]

Conventionally, in this type of memory control circuit, when data is transferred using a CPU or DMA controller, data is read from one memory and stored in a temporary register of the CPU or DMA controller, and then transferred to the other memory. When a new transfer destination address was output, that data was written to the other memory.

In the conventional example shown in FIG. 6, it is impossible to simultaneously and independently control the read signal line 16.18, write signal line 17.19 and address bus 20.21 to memories 1 and 2. Therefore, when data is transferred between two memories under the control of the CPU 3, the process shown in FIG. 7 is executed, and when DMA control is used,
The process shown in FIG. 8 was being executed. FIG. 9 is a timing chart of one word transfer when the transfer is executed by the CPU, and at this time, the address given to the transfer source memory, the address given to the transfer destination memory, and the change in read/write signal according to time. shows. Figure 10 shows DMA
It is a timing chart when control is performed by a controller. In either case, when transferring one byte, it takes one cycle to read data from the transfer source address to the data bus and write data to the temporary register, and to read and transfer data from the temporary register to the data bus. It can be seen that one additional cycle is required to write data to the destination address, and a total of two cycles are required for one operation.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, one set of memory read/write signal lines is commonly connected to two memories.
When data is transferred between two memories, there is a drawback that a read signal to the transfer source and a write signal to the transfer destination cannot be sent at the same time. Furthermore, when data is transferred between two memories, the data read from the source memory onto the data bus is stored in a temporary register under the control of the CPU or DMA controller, and then the data is stored in a temporary register. Since the contents are written to the memory of the transfer destination, the efficiency of using the data bus is approximately halved, and the disadvantage is that the memory transfer takes that much time.

The present invention improves this, and aims to make it possible to read and write between different addresses of two memories at the same time, and to significantly reduce the time required for data transfer.

[Means for solving problems]

A control means for controlling data transfer, comprising an adder inserted in the path of the address bus connected between the two memories, and a buffer inserted in each of the control lines connected between the two memories. includes means for individually controlling the buffers, and means for providing an addition value to the adder, and includes an address value to be sent to the address bus when data is transferred between two memories, and an addition value to be added to this address value. The present invention is characterized in that it includes means for simultaneously specifying the addresses of the two memories.

[For production]

Using a buffer and an adder, addresses that differ from each other by the addition value given to the adder are simultaneously designated to two memories. This makes it possible to independently control the memory read signal, memory write signal, and address bus. Therefore, data transfer of one word is completed in one cycle, and reading and writing between different addresses of two memories can be performed simultaneously, and the time required for data transfer can be significantly reduced.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 and 3 are flowcharts showing the program of the CPU 3 written in the continuous memory 4 of the embodiment of the present invention, and FIGS. FIG. 5 is a timing chart when the flowchart of the embodiment of the present invention is executed.

This device includes a CPU 3, a read-only memory 4, and a DMA controller 5 as control means for controlling data transfer between a first memory 1 and a second memory 2, and between this control means and the two memories, data bus 22
．． 23, an address bus 20.21, a buffer 25 as a control circuit, a delay inverter 6.7, and a signal line are connected.

Here, the feature of the present invention is that adders 11 are inserted in the paths of the address buses 20 and 21 connected to the second memory 2, and adders 11 are inserted in the control lines connected to the second memory 2, respectively. buffers 8.9 and 10,
The control means includes gate circuits 28, 29, and 30 as means for individually controlling the buffers 8, 9, and 10, and a latch circuit 12 for address addition and a gate circuit 32 as means for providing an added value to the adder. and the control means simultaneously specifies the addresses of the two memories 1 and 2 by an address value sent to the address bus 20.21 and an additional value added to this address value during data transfer between the two memories. It is characterized by including means.

In the present invention, the buffer 9.10 and the adder 11 provide the following:
A memory read signal 16. is transmitted independently between two memories.
18, memory write signal 17.19, address bus 20
．． It becomes possible to control 21. The delay inverter 6.7 is provided to complete writing data to the destination memory while valid data is present on the data bus.

The buffer 8.9.10 and the adder 11 simultaneously designate addresses that differ from each other by the addition value given to the adder 11 to the two memories. As a result, the memory read signal 16.18 and the memory write signal 17.19 are independently output.
, address bus 20.21. Therefore, by controlling as shown in FIG. 2, data transfer of one word is completed in one cycle as shown in FIG. 4.

Furthermore, since the program using the DMA controller 5 shown in Fig. 3 does not need to be executed before the next data transfer, high-speed data transfer is possible, and the timing chart at this time is as shown in Fig. 5. become. Especially when transferring a large amount of data, the transfer time is about half that of conventional methods, dramatically improving transfer efficiency.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to simultaneously read and write between arbitrary addresses in two memories, and the time required for data transfer can be significantly reduced.

The present invention is extremely effective when used for data transfer between two memories.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the implementation of the present invention. FIGS. 2 and 3 are flowcharts of the CPU program written in the successive memory according to the embodiment of the present invention. 4 and 5 are operation timing charts of the embodiment of the present invention. FIG. 6 is a block diagram of a conventional example. FIG. 7 and FIG. 8 are program flowcharts of a conventional example. 9 and 10 are operation timing charts of the conventional example. 1.2...Memory, 3...CPU, 4...Read-only memory, 5...DMA controller, 6.7...
Delay inverter, 8.9.10... Memory read/write signal buffer for memory 2, 11... Adder, 12... Latch circuit for address addition, 13...
・Memory-to-memory data transfer enable signal (ENB) by the CPU, 14...Address enable signal (AEN) during DMA controller operation, 15...
DMA:] controller end of process signal (
EOP), 16... Read signal line to memory 1, 17
...Write signal line to memory 1, 18...Memory 2
Read signal line to memory 1, 19... Write signal line to memory 2, 20... Address bus to memory 1, 21...
address bus to memory 2, 22... data bus to memory 1, 23... data bus to memory 2, 25.
...Buffer, 28.29.30.32...Gate circuit, 31...Delay inverter.

Claims (1)

[Claims] (1) comprising control means (3, 4, 5) for controlling data transfer between the first memory (1) and the second memory (2);
In a memory control circuit in which a data bus, an address bus, and a control circuit are connected between the control means and the two memories, an adder ( 11); buffers (8, 9, 10) respectively inserted into the control lines connected to the second memory; the control means includes means for individually controlling the buffers; and means for providing an addition value to an adder, and the control means controls the address of the two memories by the address value sent to the address bus and the addition value added to this address value when data is transferred between the two memories. A memory control circuit comprising means for simultaneously specifying.