JPS6217873A - Image processing system - Google Patents
Image processing systemInfo
- Publication number
- JPS6217873A JPS6217873A JP15605385A JP15605385A JPS6217873A JP S6217873 A JPS6217873 A JP S6217873A JP 15605385 A JP15605385 A JP 15605385A JP 15605385 A JP15605385 A JP 15605385A JP S6217873 A JPS6217873 A JP S6217873A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- image processing
- processed
- data
- host
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Processing Or Creating Images (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は端末装置等における画像処理に関し。[Detailed description of the invention] [Industrial application field] The present invention relates to image processing in terminal devices and the like.
特に高速化制御方式に関する。In particular, it relates to high-speed control methods.
従来、この種の画像処理は、第3図に示すように、ホス
)Hと画像処理部IPとの間にインプットバッファIB
(以下、バッファIBと略称する)とアウトプットバッ
ファOB(以下、バッファOBと略称する)をそれぞれ
1つづつ持っている。Conventionally, this type of image processing has been performed using an input buffer IB between a host (host) H and an image processing unit IP, as shown in FIG.
(hereinafter abbreviated as buffer IB) and output buffer OB (hereinafter abbreviated as buffer OB).
制御はホストHより被処理データをバッファIBに書き
込み、書き込み終了後バッファIBを読み出し画像処理
部IPにて処理してバッファOBに書き込み、書き込み
終了後ホス)Hより処理後のデータをバッファOBから
読み出すシリアルな制御となっていた。The control is to write the data to be processed from the host H to the buffer IB, and after the writing is completed, read the buffer IB, process it in the image processing unit IP, and write it to the buffer OB.After the writing is completed, the processed data is written from the buffer OB by the host It was a serial read control.
上述した従来の画像処理は、ホス)HよりバッファIB
、バッファOBをアクセス中2画像処理部IPでの処理
が一時中断され、逆に2画像処理部IPで処理中ホスト
HよりバッファI B 、−4ソフアOBへのアクセス
が禁止されるので、互いに処理をシリアルにしか行えな
いという欠点があった。In the conventional image processing described above, the buffer IB is
, processing in the 2nd image processing unit IP is temporarily interrupted while accessing the buffer OB, and conversely, access to the buffers IB and -4 software OB from the host H being processed in the 2nd image processing unit IP is prohibited. The drawback was that processing could only be done serially.
本発明はこのような欠点を解消しようとするものである
。The present invention seeks to eliminate these drawbacks.
本発明の画像処理方式は、バッファIB及びバッファO
Bをそれぞれ2重化構成にしたことを特徴とする。The image processing method of the present invention includes buffer IB and buffer O.
A feature is that each of B has a duplex configuration.
次に2本発明の実施例について図面を参照して説明する
。Next, two embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
本発明の画像処理方式はダブル・ぐノ7ア構成によるバ
ッファIBO,rB1とバッファOBO。The image processing method of the present invention uses buffers IBO and rB1 and buffers OBO with a double-gun configuration.
OBI及び画像処理部IPから構成されている。It is composed of OBI and an image processing unit IP.
第2図は本方式の制御動作を説明するだめの処理タイム
チャートである。時刻t。でホス) Hより被処理デー
タを・ぐノファIBOに書き込む。書き込み終了後t1
でバッファIBOを読み出すとともに5画像処理部IP
で処理しながらバッファOBOに書き込む。時刻t2で
今度はバッファTBIにホス)Hより被処理データを書
き込む。FIG. 2 is a processing time chart for explaining the control operation of this method. Time t. (H) Write the data to be processed to Gunofa IBO from H. t1 after writing is completed
At the same time as reading the buffer IBO, the 5 image processing unit IP
Write to buffer OBO while processing. At time t2, the data to be processed is written from the host (H) to the buffer TBI.
書き込み終了後t3でバッファIB1を読み出すととも
に2画像処理部IPで処理しながら今度はバッファOE
1に書き込む。これと同時にホストHよね処理後のデー
タをパソンアOBOから読み出す。時刻t4で再びホス
)Hより被処理データをバッファI B Oに書き込む
。以下同様に被処理データがなくなる寸で繰返す。After writing is completed, at t3, the buffer IB1 is read out, and while processing is performed by the second image processing unit IP, the buffer OE is read out.
Write to 1. At the same time, the data after the host H data processing is read from the pathson A OBO. At time t4, the data to be processed is again written from the host (H) to the buffer IBO. The process is repeated in the same manner until there is no more data to be processed.
以上説明17たように本発明は、ポスl−Hと画像処理
部IPとの間のインフ0ソトパノファTB及びアウトプ
ノトノZノフy’OBをぞねぞれりゞプルバッファにす
ることに」=す、ホスl−HからのバッファIB及びバ
ッファORへのアクセスと画像処理部IPでの処理を・
9ラレルに行えるとともに1画像処理部での処理を継続
的に行えるので9画像処理を高速に実行できる効果があ
る3゜As explained above, in the present invention, the input panel TB and the output panel Z'OB between the post IH and the image processing unit IP are made into a pull buffer. , access to buffer IB and buffer OR from host L-H and processing at image processing unit IP.
3° has the effect of being able to perform 9 image processing at high speed since it can be performed in 9 parallels and processing can be performed continuously in one image processing section.
第1図は本発明の一実施例のブロック図、第2図は本方
式の制御動作を説明するだめの処理タイツ・チャー1・
図、第3図は、従来の画像処理方式のブロック図。
図中、Hはホスl−、IPは画像処理部、TB。
IBo、1131 :インゾノトパノファ、OB。
OBO、OBI :アウトプノトパノファ。FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a processing tights chart 1 for explaining the control operation of this system.
FIG. 3 is a block diagram of a conventional image processing method. In the figure, H is a host l-, IP is an image processing unit, and TB. IBo, 1131: Inzonotopanopha, OB. OBO, OBI: Outpnotopanofa.
Claims (1)
像処理部との間のインプットバッファ及びアウトプット
バッファがそれぞれ2重化構成となっていることを特徴
とする画像処理方式。1. In image processing in a terminal device or the like, an image processing method characterized in that an input buffer and an output buffer between a host and an image processing section each have a duplex configuration.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15605385A JPS6217873A (en) | 1985-07-17 | 1985-07-17 | Image processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15605385A JPS6217873A (en) | 1985-07-17 | 1985-07-17 | Image processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6217873A true JPS6217873A (en) | 1987-01-26 |
Family
ID=15619279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15605385A Pending JPS6217873A (en) | 1985-07-17 | 1985-07-17 | Image processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6217873A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01303575A (en) * | 1988-05-31 | 1989-12-07 | Nec Corp | Video data processor |
JPH0438662U (en) * | 1990-07-31 | 1992-03-31 |
-
1985
- 1985-07-17 JP JP15605385A patent/JPS6217873A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01303575A (en) * | 1988-05-31 | 1989-12-07 | Nec Corp | Video data processor |
JPH0438662U (en) * | 1990-07-31 | 1992-03-31 |
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