JPS6381557A - Dual port memory - Google Patents

Abstract

PURPOSE:To remarkably reduce the data transfer time by applying memory access from both ports simultaneously in a multi-CPU system. CONSTITUTION:In case of data transfer according to the address inputted from the port A, the head address and capacity of a dual port memory C31 and a dual port memory D32 are designated to an address comparator 41. The designation is applied by the jumper setting or the setting by a CPU. Through the designation, the address comparator 41 decides the dual port memory represented by the inputted address and in case of the access to the dual port memory C31, an ENABLE(C) is outputted and in case of the access to the dual port memory D32, an ENABLE(D) is outputted to attain the access to each dual port memory.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a dual port memory used for 5 data transfer in a 5 image processing apparatus or the like, and more particularly to a dual port memory capable of speeding up data transfer.

Prior Art Conventionally, in data transfer in a multi-CPU system,
A dual port memory is provided between the two buses, and this is used as a buffer to receive and pass data. However, with this method, while a controller on one bus is accessing memory, a controller on the other bus cannot access the memory.

For example, as shown in Figure 4, a control signal.

If the address and address are given, data can be read/written to the dual port memory, but the second
As shown in the figure, if port A side is executing read/write of data 1 and 2, it cannot be accessed from port B side, and port B side is executing read/write of data 1 and 2. Then, access from the port A side becomes impossible.

For this reason, it has been difficult to speed up data transfer in multi-CPU systems and the like.

the purpose The purpose of the present invention is to improve these problems.

An object of the present invention is to provide a dual port memory capable of speeding up data transfer in a multi-CPU system or the like.

Configuration To achieve the above object, the dual port memory of the present invention connects ports on both sides of the dual port memory to the dual port memory.

In a multi-CPU system that accesses the dual-port memory by sending address, data, and control signals, the dual-port memory is divided into a plurality of parts, and the address, data, and control signals input from the port are
and means for controlling control signals (gate group);
and a means (address comparator) for determining the dual port memory specified by the address, and when an address is input from one of the ports, the address comparator determines the dual port memory specified by the address. Then, the gate group enables the control signal, accesses the designated dual port memory from that port, and at the same time accesses a dual port memory other than the designated dual port memory from the other of both ports. It is characterized by doing the following.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a multi-CPU system in an embodiment of the present invention, FIG. 2 is an explanatory diagram of data transfer timing in an embodiment of the present invention, and FIG. 3 is a diagram of a multi-CPU system in an embodiment of the present invention. 3 is a data transfer flowchart of the system.

As shown in FIG. 1, the multi-CPU system of the present invention includes dual port memory C31, dual port memory D3
2. It includes gate groups 11, 12, 21° 22, and address comparators 41, 42.

Gate group 11. and gate group 12 apply address, data, and control signals from the port A side to dual port memory C9 and dual port memory D, respectively, and gate group 21° and gate group 22,
Address, data, and control signals from the port B side are applied to dual port memory C2 and dual port memory D, respectively.

Further, the address comparator 41 determines whether the address information input from the port A side is an access to the dual port memory C or the dual port memory D, and the address comparator 42 determines whether the address information input from the port A side is an access to the dual port memory C or the dual port memory D.
It is determined whether the address information input from the side is an access to dual port memory C or dual port memory D.

In the multi-CPU system of this embodiment, when data is transferred according to the address input from the port A side, first, the address comparator 41 is connected to the dual port memory C.
31, and the start address and capacity of the dual port memory D32. This designation is a jumper setting,
Alternatively, it is performed by setting from the CPU.

With this specification, the address comparator 41 can determine the dual port memory indicated by the input address, and outputs ENABLE (C) if the access is to the dual port memory C31, and outputs ENABLE (C) if the access is to the dual port memory D32. ENABLE(D)
is output, allowing access to each dual port memory. Note that the address comparator 42 similarly determines the dual port memory indicated by the address input from port B, and selects the dual port memory indicated by the address input from port B.
If the access is to 1, output ENABLE (C'), and if the access is to the dual port D32,
Outputs ENABLE(D').

For example, as shown in FIG. 3, when an address is input from the port A side, the address comparator 41 determines the designated dual port memory to be accessed, and the gate group 11
Outputs ENABLE(C) to The dual port memory C31 has data transfer timing as shown in Fig. 2.
Writes n bytes of data 1 received from the port A side via the gate group 11 (301), and notifies the port B side that reading is possible (302).

Next, the port A side writes data 2 to the dual port memory D32 (303). Further, in parallel with this process, the port B side reads data 1 stored in the dual port memory C31 (304).

In this way, data 2 is stored in the dual port memory D32.
When the byte is written, the port B side is notified again that reading is possible (305).

Furthermore, data 3 is written to the dual port memory C31 (306).

In response to this notification, in parallel with data writing to the dual port memory C31, the port B side reads data 2 written to the dual port memory D32 (30
7).

In this way, by using the dual port memory in a multi-CPU toggle configuration and repeating the above operations, one port side is being accessed.

Data can be transferred at high speed without the other port having to wait, and the transfer time can be significantly shortened, especially when a large amount of data, such as image data, is to be transferred.

In this embodiment, data is written from one port and data is read from the other port, but the same effect can be obtained in the reverse case.

Effects According to the present invention, in a multi-CPU system, memory access can be performed from both ports simultaneously, and data transfer time can be significantly shortened.

[Brief explanation of the drawing]

The first part is a configuration diagram of a multi-CPU system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of data transfer timing in an embodiment of the present invention, and FIG. Child group, 31; Dual port memory C, 32: Dual port memory D, 41, 42 Near address comparator・* Dipeso collar "-1'---) -1-55-1) +t+
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Figure 3

Claims (1)

[Claims] 1. In a multi-CPU system that accesses the dual-port memory by sending address, data, and control signals to the dual-port memory from ports on both sides of the dual-port memory, dividing the dual-port memory into a plurality of parts, comprising means for controlling the address, data, and control signal input from the port, and means for determining a dual port memory designated by the address, when the address is input from one of the ports; The determining means determines the dual port memory specified by the address, and the control means enables the control signal, accesses the designated dual port memory from one of the ports, and simultaneously performs the access. A dual port memory characterized in that a dual port memory other than the designated dual port memory is accessed from the other of both ports.