JPS63100553A - High-speed transferring system between memory blocks - Google Patents

Abstract

PURPOSE:To improve the throughput of a microcomputer system by providing the function which equalizes the transfer source address and the transfer destination address in case of transfer between memory blocks. CONSTITUTION:In case of transfer between memory blocks 6 and 7, the transfer source memory and the transfer destination memory are selected by memory addresses outputted from a DAM control LSI 3, and a signal MEMW or MEMR is sent to one memory IC, and a signal IOR or IOW is sent to the other memory IC. Since the transfer source memory outputs data onto a data bus by the leading edge of the signal MEMR or IOR and data on the data bus is inputted to the transfer destination memory by the trailing edge of the signal IOW or MEMW, data is transferred from the transfer source memory to the transfer destination memory in one DMA cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer system that requires transfer between memory blocks, and particularly to a transfer source memory block.

The present invention relates to a high-speed transfer method between memory blocks suitable for a microcomputer system in which the destination memory block and the transfer destination memory block are configured with separate memory ICs.

[Conventional technology]

Conventionally, in order to perform transfer between memory blocks using a DMA control LSI, data is read from the transfer source memory and written to a temporary storage buffer in the first DMA cycle, and data is written in the temporary storage buffer in the second DMA cycle.
It is known that the A cycle has temporary memory, and the existing DM
The A control LSI also performed transfer between memory blocks using this method.

Although the conventional method is fast because it does not involve the MPU,
Since one transfer requires two DMA cycles, it took longer than transfer between memory and I/O.

[Problem that the invention seeks to solve]

In the conventional example described above, there was a problem in that it took time to transfer data between memory blocks, reducing the throughput of the microcomputer system.

In a transfer between memory blocks to which memory ICs are allocated separately, the present invention replaces reading from the source memory and writing to the destination memory, which conventionally took two DMA cycles, between the memory and the I/O. The purpose is to speed up the transfer between memory blowers and improve the throughput of the microcomputer system by completing the transfer in one DMA cycle, similar to the transfer of .

Means for Solving Problem C] The above purpose is to make the address of the transfer source memory and the address of the transfer destination memory the same during transfer between memory blocks, and to
By sharing the address generated by the A control LSI between two memory blocks and selecting the transfer source memory and transfer destination memory at the same time, reading from the transfer source memory and writing to the transfer destination memory can be performed in one DMA cycle. Since the transfer between memory blocks can be made faster, the throughput of the microcomputer system can be improved.

[Effect]

Generally, in the case of a read operation, a memory IC selects a specific address within the memory IC using an address and a memory IC selection signal, and then reads data at the leading edge of a pulsed strobe signal to read data from the memory. In the case of a write operation, after selecting a specific address in the memory IC using the address and memory IC selection signal, the data bus is output at the trailing edge of a pulsed strobe signal for writing data to the memory. Enter the data. In addition, the existing DMA control LSI uses a DMA transfer response signal DACK, a memory address, a strobe signal MEMR for reading data from memory, and a strobe signal for writing data to I/O in one DMA cycle. A strobe signal IOR for reading data from the signal IOW or I/O and a strobe signal MEMV for writing data into the memory are output. In transfer between memory blocks, the transfer source memory and transfer destination memory are selected by the memory address output by the DMA III control LSI, and the MEMW signal or MEMR signal is sent to one memory IC and the other memory IC. By inputting the IOR signal or the IOW signal, the transfer source memory receives the MEMR signal or the IOR signal.
Data is output onto the data bus at the leading edge of the signal, and data on the data bus is input to the destination memory at the trailing edge of the IOW signal or the MEMV signal, so one DMA cycle transfers data from the source memory to the destination memory. Data transfer to memory becomes possible.

〔Example〕

An embodiment of the present invention will be described below. Fig. 1 shows a 20'' diagram of the present invention, Fig. 2 shows a concrete embodiment of the vine transfer control circuit 2 and the memory IC selection signal switching circuit 5, and Fig. 3 shows a concrete embodiment of the present invention. A timing chart of this embodiment is shown.

Memory block A6 and memory block B7 are composed of separate memory ICs. Further, the address decoder 4 outputs a memory block A selection signal 15 and a memory block Bfi selection signal 16 at different addresses. In cases other than transfer between memory blocks, memory block B7 is selected by the memory block B selection signal 16 by the function of the memory IC selection signal switching circuit 5, so it is assigned to a different address from the memory block A6, and the memory output from the MPU 1 is A read/write signal 24 is used to read data from or write data to the memory.

When the MPUI sets the memory block transfer request signal /O to the flip-flop 21 of the memory block transfer control circuit 2, the flip-flop 21 transfers D to the DMA control LSI 3.
Issue MA request compensation number 11.

:'Du>AmwLS I 3+1puaa request-sl
1*When accepted, it issues an MPU hold request signal 12 to MPtJl, and when MPUI accepts this, it sets the address output and data output to high impedance and sets the address bus 8. In addition to disconnecting from the data bus 9, the output of the memory read/write signal 24 is also set to high impedance, and the right to use the bus and read/write control to the memory is controlled by the DMA control L.
When the DMA control LSI 3 receives the MPU hold response signal 13, it returns the DMA response signal 14 to the memory block transfer control circuit 2 and sends the MPU hold response signal 13 to the address bus 8.
Then, the address signal 22 of the memory block A6, which has been programmed in the DMA control LSI 3 in advance, is output.

Address decoder 4 outputs memory block A selection signal 15 in response to address signal 22 and selects memory block A6. In addition, the memory block transfer control circuit 2
The C selection switching signal 17 is sent to the memory IC selection signal switching circuit 5, and the memory IC selection signal switching circuit 5 is switched to select the memory block B7 with the memory block A selection signal 15, and the memory block 86 and memory block B7 are switched. is selected by the address signal 22 output from the DMA control LSI 3. When memory block A6 is the transfer source and memory block B7 is the transfer destination, the strobe signal 18 is a signal MEMR for reading data from the memory, and the strobe signal 19 is a signal for writing data to It is IOW. Memory block 86 receives strobe signal 1
The transfer data signal 23 is output to the data bus 9 at the leading edge of the strobe signal 19, and the memory block B7 writes the transfer data signal 23 on the data bus 9 to the memory at the trailing edge of the strobe signal 19, thus completing one DMA cycle. Furthermore, when memory block B7 is the transfer source and memory block A6 is the transfer destination, the strobe signal 18 is the signal MEMIII for writing data to the memory, and the strobe signal 19 is for reading data from the I/O. is the signal IOR of At this time, strobe signal 1 in the timing chart of Figure 3.
8 and the strobe signal 19 are inverted.

Memory block B7 outputs the transfer data signal 23 to the data bus 9 at the leading edge of the strobe signal 19, and memory block B86 writes the transfer data signal 23 on the data bus 9 to the memory once at the trailing edge of the strobe signal 18. DMA cycle ends. When memory block A6 is the transfer source, DMA control LSI3 is programmed to transfer from memory to Ilo, and when memory block B7 is the transfer source, DMA control LSI3 is programmed to transfer from I/O to memory. Then, the DMA control LSI automatically switches the contents of the strobe signal 18 and strobe signal 19.

Since the DMA request signal 11 remains active until the number of block transfers preprogrammed in the DMA control LSI is completed, the DMA cycle continues. In the last DMA cycle that ends the number of block transfers, the DMA control LSI issues a block transfer end signal 20 together with the DMA response signal 14.

Flip-flop 2 in memory block transfer control circuit 2
1 is reset by the AND of the DMA response signal 14 and block transfer end signal 20, resets the DMA request signal 11, and ends the memory block transfer.

According to this embodiment, reading from the source memory and writing to the destination memory can be completed in one DMA cycle in inter-memory block transfer. Furthermore, in this embodiment, the strobe signal switching circuit 24 is configured with a circuit similar to the memory IC selection signal switching circuit 5, and the memory IC selection switching signal 17 is connected to the DMA response signal 14. If data transfer between memory blocks B7 and 1/O occurs during data transfer between memory blocks B7 and 1/O by a DMA request with a higher priority than DMA request signal 11 by memory block transfer request signal /O, memory block transfer request signal /O The DMA response signal 14 corresponding to the DMA request signal 11 is not output, and the memory I connected to it is not output.
Since the C selection switching signal 17 is not output, the MEM for reading data from or writing data to the memory
Strobe signal 18, R or MEMR, is connected to memory block B7 through strobe signal switching circuit 24. Therefore, as mentioned above, even if a data transfer between memory blocks B7 and 1/O occurs due to a DMA request with a higher priority than the DMA request signal 11 caused by the memory block transfer request signal /O during transfer between memory blocks, it can be handled. can.

〔Effect of the invention〕

According to the present invention, the transfer between memory blocks using a DMA control LSI requires two DMA cycles to transfer one data, but it can be shortened to one DMA cycle. This has the effect of cutting the time in half and improving the throughput of the microcomputer system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram of a memory block transfer control circuit and memory IC selection signal switching circuit, which are important parts of the present invention, and FIG. 3 is a timing chart of this embodiment. It is. DESCRIPTION OF SYMBOLS 1...MPU, 2...Memory block transfer control circuit, 3...DMA control LSI, 4...Address decoder, 5...Memory IC selection signal switching circuit, 6...
Memory block A, 7...Memory block B, 8...
・Address signal, 9...Data bus, /O...Memory block transfer request signal, 11...DMA request code, 12...MPU hold request signal, 13...MP
tJ hold response signal, 14...DMA response signal, 1
5...Memory block A selection signal, 16...Memory block B selection signal, 17...Memory IC selection switching signal, 18...Strobe signal, 19...Strobe signal, 20...Block transfer End signal, 21...Flip-flop, 22...Address signal, 23...
Transfer data signal, 24... Strobe signal switching circuit.

Claims (1)

[Claims] 1. 2 memory blocks composed of separate memory ICs
A strobe signal output for writing data to the memory during data transfer between the memory and the I/O, a strobe signal output for reading data from the memory, and an I/O
strobe signal output for reading data from /O,
Transfer between memory blocks in a microcomputer system that has an existing DMA control LSI that has a strobe signal for writing data to I/O and a signal output to notify that a preset number of data transfers have been completed. A high-speed transfer method between memory blocks characterized by having a function of making a transfer source address and a transfer destination address the same.